IEEE Transactions on Computers

Issue 11 • Nov. 1981

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  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1981, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1981, Page(s): c2
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  • Introduction

    Publication Year: 1981, Page(s):821 - 822
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1493 KB)

    THIS IS the first Special Issue of the IEEE TRANSACTIONS on Design for Testability, jointly sponsored by the IEEE Computer Society and the IEEE Circuits and Systems Society. Both of these organizations have had a continuing interest in this topic, as demonstrated by the publication of papers in their respective TRANSACTIONS, and by their support of such workshops as CANDE and the IEEE Workshop on ... View full abstract»

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  • A Design of Programmable Logic Arrays with Universal Tests

    Publication Year: 1981, Page(s):823 - 828
    Cited by:  Papers (78)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2204 KB)

    In this paper the problem of fault detection in easily testable programmable logic arrays (PLA's) is discussed. The easily testable PLA's will be designed by adding extra logic. These augmented PLA's have the following features: 1) for a PLA with n inputs and m columns (product terms), there exists a "universal" test set such that the test patterns and responses do not depend on the function of th... View full abstract»

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  • A Hardware Approach to Self-Testing of Large Programmable Logic Arrays

    Publication Year: 1981, Page(s):829 - 833
    Cited by:  Papers (38)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1929 KB)

    A hardware technique for testing large programmable arrays is presented. The method is based on an appropriate circuit partitioning and on using nonlinear feedback shift registers for test pattern generation. It allows the testing of a PLA within a number of cycles that is a linear function of the number of inputs and product terms. A 8 X 16 X 8 PLA is completely tested within 52 cycles; a 16 X 48... View full abstract»

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  • A Testable Design of Iterative Logic Arrays

    Publication Year: 1981, Page(s):833 - 841
    Cited by:  Papers (73)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4211 KB)

    Testable design of unilateral iterative logic arrays (ILA) of combinational cells under the assumption of a single cell failure is considered. The concepts of one-step testability and one-step C-testability are introduced. Methods to modify the basic cell flow table so as to facilitate fault detection and location are given. It is shown that if no directly observable outputs from each cell are ava... View full abstract»

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  • Design of Easily Testable Bit-Sliced Systems

    Publication Year: 1981, Page(s):842 - 854
    Cited by:  Papers (71)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5228 KB)

    Bit-sliced systems are formed by interconnecting identical slices or cells to form a one-dimensional iterative logic array (ILA). This paper presents several design techniques for constructing easily testable bit-sliced systems. Properties of ILA's that simplify their testing are examined. C-testable ILA's, which require a constant number of test patterns independent of the array size, are charact... View full abstract»

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  • Multiple Fault Testing of Large Circuits by Single Fault Test Sets

    Publication Year: 1981, Page(s):855 - 865
    Cited by:  Papers (44)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3219 KB)

    A general theory is presented in this paper to quantitatively predict the multiple fault coverage capability of single fault detection test sets in combinational circuits. The theory is unique in that it provides greatest lower bounds on the coverage capability of all possible circuits of concern by a simple table-look-up process. All the results known so far in this area are seen to be special ca... View full abstract»

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  • Design for Autonomous Test

    Publication Year: 1981, Page(s):866 - 875
    Cited by:  Papers (140)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2978 KB)

    A technique for modifying networks so that they are capable of self test is presented. The major innovation is partitioning the network into subnetworks with sufficiently few inputs that exhaustive testing of the subnetworks is possible. View full abstract»

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  • Design of Testable Structures Defined by Simple Loops

    Publication Year: 1981, Page(s):875 - 884
    Cited by:  Papers (13)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4088 KB)

    A methodology is given for generating combinational structures from high-level descriptions (using assignment statements, "if" statements, and single-nested loops) of register-transfer (RT) level operators. The generated structures are cellular, and are interconnected in a tree structure. A general algorithm is given to test cellular tree structures with a test length which grows only linearly wit... View full abstract»

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  • New Measures of Testability and Test Complexity for Linear Analog Failure Analysis

    Publication Year: 1981, Page(s):884 - 888
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3272 KB)

    The failure analysis of analog electronic systems is characterized by numerous, difficult problems. Assessing the testability and test complexity of a given system is one such problem. In fact, robust, quantitative measures of these important features have not been available to the analog testing community. This paper introduces new measures for both testability and test complexity which: 1) are q... View full abstract»

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  • Diagnosability of Nonlinear Circuits and Systems—Part I: The dc Case

    Publication Year: 1981, Page(s):889 - 898
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3018 KB)

    A theory for the diagnosabilty of nonlinear dc circuits (memoryless systems) is developed. Based on an input-output model, a necessary and sufficient condition for the local diagnosability of the system, which is a rank test on a matrix, is derived. Various ways of reducing the computational complexity of this test are indicated. A sufficient condition for single fault diagnosability, which is muc... View full abstract»

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  • Diagnosability of Nonlinear Circuits and Systems—Part II: Dynamical Systems

    Publication Year: 1981, Page(s):899 - 904
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2076 KB)

    A theory for the diagnosability of nonlinear dynamical systems, similar to the one in Part I[1] for memoryless systems, is developed. It is based on an input-output model of the system in a Hilbert space setting. A necessary and sufficient condition for the local diagnosability of the system, which is a rank test on a matrix, is derived. A simple sufficient condition is also derived. It is shown t... View full abstract»

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  • IEEE Transactions on Computers Planned Special Issues

    Publication Year: 1981, Page(s): 904
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  • Students in Computer Science and Engineering!

    Publication Year: 1981, Page(s): 904
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  • IEEE Computer Society Publications

    Publication Year: 1981, Page(s): 904
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  • Call for Papers Trends and Applications

    Publication Year: 1981, Page(s): 904
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org