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IEEE Transactions on Computers

Issue 10 • Date Oct. 1981

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Displaying Results 1 - 21 of 21
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1981, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1981, Page(s): c2
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  • A DAG-Based Algorithm for Prevention of Store-and-Forward Deadlock in Packet Networks

    Publication Year: 1981, Page(s):709 - 715
    Cited by:  Papers (51)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2712 KB)

    Store-and-forward deadlock (SFD) occurs in packet- switched computer networks when, among some cycle of packets buffered by the communication system, each packet in the cycle waits for the use of the buffer currently occupied by the next packet in the cycle. Several techniques for the prevention of SFD are known, but all exact some cost in terms of efficient and flexible packet handling. An ideal ... View full abstract»

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  • The Memory System of a High-Performance Personal Computer

    Publication Year: 1981, Page(s):715 - 733
    Cited by:  Papers (7)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (7589 KB)

    The memory system of the Dorado, a compact high- performance personal computer, has very high I/O bandwidth, a large paged virtual memory, a cache, and heavily pipelined control; this paper discusses all of these in detail. Relatively low-speed I/O devices transfer single words to or from the cache; fast devices, such as a color video display, transfer directly to or from main storage while the pr... View full abstract»

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  • Congestion Control of Packet Communication Networks by Input Buffer Limits—A Simulation Study

    Publication Year: 1981, Page(s):733 - 742
    Cited by:  Papers (12)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4392 KB)

    An experimental study was conducted using a network simulator to investigate the performance of packet communication networks as a function of: the network resource capacities (channels, buffers), the network load (number of virtual channels, virtual channel loads), protocols (flow control, congestion control, routing), and protocol parameters (virtual channel window size, input buffer limits). Pe... View full abstract»

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  • Fault-Diagnosis for a Class of Multistage Interconnection Networks

    Publication Year: 1981, Page(s):743 - 758
    Cited by:  Papers (88)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2646 KB)

    To study the fault-diagnosis method for a class of multistage interconnection networks a general fault model is first constructed. Specific steps for diagnosing single faults and detecting multiple faults in interconnection networks such as the indirect binary n-cube network and the flip network are then developed. The following results are derived in this study: 1) independent of the network size... View full abstract»

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  • Error Complexity Analysis of Algorithms for Matrix Multiplication and Matrix Chain Product

    Publication Year: 1981, Page(s):758 - 771
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2849 KB)

    The error complexity analysis of three algorithms for matrix multiplication and matrix chain product has been given. It is shown that the usual inner product type algorithm is by far the best algorithm for simple matrix multiplication or matrix chain product in terms of minimal basic term growth and minimal error complexities, the latter being independent of the order of pairwise matrix multiplica... View full abstract»

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  • Performance of Processor-Memory Interconnections for Multiprocessors

    Publication Year: 1981, Page(s):771 - 780
    Cited by:  Papers (462)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4002 KB)

    A class of interconnection networks based on some existing permutation networks is described with applications to processor to memory communication in multiprocessing systems. These networks, termed delta networks, allow a direct link between any processor to any memory module. The delta networks and full crossbars are analyzed with respect to their effective bandwidth and cost. The analysis shows... View full abstract»

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  • On the Buffer Behavior with Poisson Arrivals, Priority Service, and Random Server Interruptions

    Publication Year: 1981, Page(s):781 - 786
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1974 KB)

    A discrete buffered system with infinite buffer size, multiple Poisson arrival streams, priority service, and random server interruptions is considered. The queueing times of the data packets of different priority classes are derived using the concepts of delayed busy cycle and level crossing analysis. The results of this study can be used as a guidelines for the buffer design in digital systems. View full abstract»

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  • An Optimal Algorithm for Scheduling Requests on Interleaved Memories for a Pipelined Processor

    Publication Year: 1981, Page(s):787 - 800
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4013 KB)

    In this paper an optimal algorithm for scheduling requests on interleaved memories is presented. With this algorithm the average completion time for servicing a finite set of randomly generated requests is proved to be minimum. Performance of this algorithm for nonrandom requests has not been proved. However, it is compared with alternate algorithms using simulations. A pipelined processor is used... View full abstract»

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  • A Hard Programmable Control Unit Design Using VLSI Technology

    Publication Year: 1981, Page(s):800 - 810
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4580 KB)

    Microprogramming has become a widely used technique which brings versatility to the control unit of a digital system. However, since all microcommands contained in a microinstruction are changed simultaneously, this form of control requires the coding of all possible combinations of parallel commands as separate microinstructions. This causes the resulting microprograms to become space- and timewi... View full abstract»

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  • An Improvement of Reliability of Memory System with Skewing Reconfiguration

    Publication Year: 1981, Page(s):811 - 812
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (349 KB)

    In a memory system with skewing reconfiguration, a virtual memory address is encoded by an address encoder to avoid using a faulty memory area. This correspondence shows one method to improve the reliability of the address encoder by encoding a virtual memory address together with data to an error correcting code. Only a few additional gates are required for the implementation if the memory system... View full abstract»

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  • Comments on "Concurrent Search and Insertion in AVL Trees"

    Publication Year: 1981, Page(s): 812
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (221 KB)

    Ellis' concurrent AVL insertion algorithm1is discussed in this correspondence. We note that obtaining a block of storage for the new AVL leaf may become a serial bottleneck for the entire insertion algorithm. We indicate a potential solution and refer the reader to another paper [1] in which the full details are given. View full abstract»

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  • Correction to "Complete Solution of Boolean Equations"

    Publication Year: 1981, Page(s): 812
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  • The Degradation in Memory Utilization Due to Dependencies

    Publication Year: 1981, Page(s):813 - 818
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1217 KB)

    In this correspondence we have presented a technique to find the degradation in memory and buffer utilization due to dependencies of accesses issued by a pipelined computer. When a dependency occurs, the request stream to the memory is interrupted and the utilization of the memory decreases. The dependency is then resolved in the pipelined computer. New requests are generated and the utilization g... View full abstract»

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  • Correction to "The Mpg System: A Machine-Independent Efficient Microprogram Generator"

    Publication Year: 1981, Page(s): 818
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  • Correction to "Dual-Mode Logic for Function-Independent Fault Testing"

    Publication Year: 1981, Page(s): 819
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  • Correction to "An Efficient Method for Improving Reliability of a Pipeline FFT"

    Publication Year: 1981, Page(s): 819
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (63 KB)

    The following errors should be noted in the above correspondence.1 View full abstract»

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  • Planned Special Issues IEEE Transactions on Computers

    Publication Year: 1981, Page(s): 819
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  • IEEE Computer Society Publications

    Publication Year: 1981, Page(s): 819
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  • Call for Papers Trends and Applications

    Publication Year: 1981, Page(s): 819
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org