IEEE Transactions on Computers

Issue 9 • Sept. 1980

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  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1980, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1980, Page(s): c2
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  • Editor's Notice

    Publication Year: 1980, Page(s): 761
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  • Foreword Parallel Processing Today

    Publication Year: 1980, Page(s):762 - 763
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1523 KB)

    THE PAPERS that follow in this Special Issue on Parallel Processing were originally presented at the 1979 International Conference on Parallel Processing [1]. Other important papers from that conference could not be included in this issue because of space or time limitations. We hope that at least some of them will appear as regular papers in future issues of this TRANSACTIONS and other publicatio... View full abstract»

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  • High-Speed Multiprocessors and Compilation Techniques

    Publication Year: 1980, Page(s):763 - 776
    Cited by:  Papers (117)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4860 KB)

    The purpose of this paper is to present some ideas on multiprocessor design and on automatic translation of sequential programs into parallel programs for multiprocessors. With respect to machine design, two subjects are discussed. First, a multiprocessor allowing parallelism at a very low level is sketched and then, a brief discussion on the interconnection network is presented. View full abstract»

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  • A Uniform Representation of Single-and Multistage Interconnection Networks Used in SIMD Machines

    Publication Year: 1980, Page(s):777 - 791
    Cited by:  Papers (24)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3471 KB)

    A switching theoretic framework for the study of interconnection networks is developed. An equivalence relationship between networks is defined. Single-stage and multistage networks that are particularly useful for single-instruction multiple-data stream (SIMD) machines are studied. It is shown that the networks form two distinct equivalence classes under this definition of equivalence relationshi... View full abstract»

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  • The Theory Underlying the Partitioning of Permutation Networks

    Publication Year: 1980, Page(s):791 - 801
    Cited by:  Papers (58)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (10297 KB)

    The age of the microcomputer has made feasible large-scale multiprocessor systems. In order to use this parallel processing power in the form of a flexible multiple-SIMD (MSIMD) system, the interconnection network must be partitionable and dynamically reconfigurable. The theory underlying the partitioning of MSIMD system permutation networks into independent subnetworks is explored. Conditions for... View full abstract»

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  • The Reverse-Exchange Interconnection Network

    Publication Year: 1980, Page(s):801 - 811
    Cited by:  Papers (70)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2174 KB)

    Properties of the reverse-exchange interconnection network are used to develop a reconfiguration scheme and a two-pass structure for enhancing the efficiency of a class of multistage interconnection networks. Functional relationships among a class of multistage interconnection networks are first derived. According to the functional relationships, we propose a reconfiguration scheme which enables a... View full abstract»

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  • Concurrent Search and Insertion in AVL Trees

    Publication Year: 1980, Page(s):811 - 817
    Cited by:  Papers (29)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2074 KB)

    This paper addresses the problem of concurrent access to dynamically balanced binary search trees. Specifically, two solutions for concurrent search and insertion in AVL trees are developed. The first solution is relatively simple and is intended to allow several readers to share nodes with a writer process. The second solution uses the first as a starting point and introduces additional concurren... View full abstract»

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  • Distributed Enumeration on Between Computers

    Publication Year: 1980, Page(s):818 - 825
    Cited by:  Papers (41)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2960 KB)

    Known solutions of a large number of important (and difficult) computational problems called NP-complete problems depend on enumeration techniques which examine all feasible alternatives. This paper considers the design of enumeration schemes in a distributed environment in an attempt to exploit the parallel activities inherent in enumeration algorithms. View full abstract»

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  • A Flow Analysis Procedure for the Translation of High-Level Languages to a Data Flow Language

    Publication Year: 1980, Page(s):826 - 831
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1168 KB)

    A data flow analysis procedure is described which may be used in the translation of high-level languages to parallel target languages. The technique analyzes the data dependencies which exist between statements in a high-level program and constructs an intermediate form amenable to optimizing transformations and code generation. View full abstract»

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  • Resource Optimization of a Parallel Computer for Multiple Vector Processing

    Publication Year: 1980, Page(s):831 - 836
    Cited by:  Papers (7)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1087 KB)

    Performance optimization of a shared-resource parallel computer is studied in this correspondence. Such a parallel computer contains multiple control units (CU's) sharing a resource pool of processing elements (PE's) and operating with multiple single-instruction-multiple-data (MSIMD) streams. A formal queueing model is proposed for MSIMD machines used in multiple array processing. Analytic result... View full abstract»

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  • Design of a Massively Parallel Processor

    Publication Year: 1980, Page(s):836 - 840
    Cited by:  Papers (419)  |  Patents (42)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2427 KB)

    The massively parallel processor (MPP) system is designed to process satellite imagery at high rates. A large number (16 384) of processing elements (PE's) are configured in a square array. For optimum performance on operands of arbitrary length, processing is performed in a bit-serial manner. On 8-bit integer data, addition can occur at 6553 million operations per second (MOPS) and multiplication... View full abstract»

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  • Efficient Function Implementation for Bit-Serial Parallel Processors

    Publication Year: 1980, Page(s):841 - 844
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (812 KB)

    Parallel processors with bit-serial processing elements (PE's) usually implement arithmetic functions by a sequence of word-level arithmetic operations; however, basic operations must be specified at the bit level. In this correspondence the possibility of more efficiently implementing a function with a special tailored sequence of bit-serial operations is considered. A general scheme is described... View full abstract»

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  • IEEE Computer Society Publications

    Publication Year: 1980, Page(s): 844
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  • Advance Announcement... Tutorial Week 80

    Publication Year: 1980, Page(s): 844
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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org