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Computers, IEEE Transactions on

Issue 8 • Date Aug. 1980

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  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1980 , Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1980 , Page(s): c2
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  • An Approach to Gate Assignment and Module Placement for Printed Wiring Boards

    Publication Year: 1980 , Page(s): 681 - 688
    Cited by:  Papers (1)
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    High-density packaging is one of the most urgent requirements in the design of digital systems. In the assembly of such systems, printed wiring boards (PWB's) are used very often to provide the necessary interconnection among circuit modules. Thus, methods to raise wirability of routers are continually under investigation. View full abstract»

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  • Multiple-Read Single-Write Memory and Its Applications

    Publication Year: 1980 , Page(s): 689 - 694
    Cited by:  Papers (3)  |  Patents (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2323 KB)  

    A multiple-read single-write (MRSW) memory is proposed as a hardware solution to the memory and bus conflict problem in distributed and multiprocessing computing systems. Each memory module is assigned to a host processor which is hardwired to its read–write channel. Its read-only channels are shared by a few closely coupled processors, I/O devices, and/or a data bus which provides access to all other processors. The exact processor-memory organization is determined by a module correlation criteria, which also yields a quantitative measure of the effectiveness of the solution. In a class of scientific computing problems where module correlation is limited to neighboring modules, the memory conflict problem is completely eliminated. The processors may operate as array processors controlled by a CPU, or they may operate autonomously with capabilities of originating programs or transactions. The location conflict problem of multiaccess memories is resolved without additional hardware or delay. View full abstract»

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  • On a Class of Multistage Interconnection Networks

    Publication Year: 1980 , Page(s): 694 - 702
    Cited by:  Papers (331)  |  Patents (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4132 KB)  

    A baseline network and a configuration concept are introduced to evaluate relationships among some proposed multistage interconnection networks. It is proven that the data manipulator (modified version), flip network, omega network, indirect binary n-cube network, and regular SW banyan network (S = F = 2) are topologically equivalent. The configuration concept facilitates developing a homogeneous routing algorithm which allows one-to-one and one- to-many connections from an arbitrary side of a network to the other side. This routing algorithm is extended to full communication which allows connections between terminals on the same side of a network. A conflict resolution scheme is also included. Some practical implications of our results are presented for further research. View full abstract»

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  • Multiprocessor Scheduling with Memory Allocation—A Deterministic Approach

    Publication Year: 1980 , Page(s): 703 - 709
    Cited by:  Papers (4)
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    This paper proposes a deterministic approach to the preemptive scheduling of independent tasks, which takes into account primary memory allocation in multiprocessor systems with virtual memory and a common primary memory. Each central processing unit (CPU) is assumed to have dedicated paging devices and thus paging- device competition does not exist in the system. The system workload is based on an analytic approximation to the lifetime curve of a task. Exact and approximate algorithms are presented which minimize or tend to minimize the length of schedules on an arbitrary number of identical processors. In the general case, the exact algorithm is based on nonlinear programming; however, the approximate algorithm requires the solution of several nonlinear equations with one unknown. For certain cases, analytical results have also been obtained. View full abstract»

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  • Job Scheduling in a Single-Node Hierarchical Network for Process Control

    Publication Year: 1980 , Page(s): 710 - 719
    Cited by:  Papers (1)
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    The operating characteristics of a typical single-node hierarchical element in a multiprocessor network such as might be used for process control are described, and the class of scheduling problems arising from the use of such a network is discussed and related to similar problems which have been reported in the literature. Two measures of system performance are then defined: the "settling time," defined as the maximum of the finishing times of all jobs when a set of jobs is initiated once in the network, and the "steady-state service," a related performance index for the case where jobs are initiated on a periodic basis. Finally, a simulation model is used to evaluate the operating characteristics of the hierarchical network using the two metrics in conjunction with several synthetic workloads; a general optimization procedure is shown to lead to values of scheduling parameters which are close to optimal even for network workloads with many degrees of freedom (i.e., when many computers are initiating jobs). View full abstract»

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  • On Evaluating the Performability of Degradable Computing Systems

    Publication Year: 1980 , Page(s): 720 - 731
    Cited by:  Papers (214)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3425 KB)  

    If the performance of a computing system is "degradable," performance and reliability issues must be dealt with simultaneously in the process of evaluating system effectiveness. For this purpose, a unified measure, called "performability," is introduced and the foundations of performability modeling and evaluation are established. A critical step in the modeling process is the introduction of a "capability function" which relates low-level system behavior to user-oriented performance levels. A hierarchical modeling scheme is used to formulate the capability function and capability is used, in turn, to evaluate performability. These techniques are then illustrated for a specific application: the performability evaluation of an aircraft computer in the environment of an air transport mission. View full abstract»

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  • A Method for Minimizing Incompletely Specified Sequential Machines

    Publication Year: 1980 , Page(s): 732 - 736
    Cited by:  Papers (1)
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    After Paull and Unger introduced the problem of state minimization in incompletely specified sequential machines (ISSM's), its increasing importance and complexity induced many people to continue research related to this field. Here we shall present a method for obtaining a minimum form of a given ISSM by application of a directed tree graph. In order to save counting effort for a minimum form, we extend the concept of erasure from a relation between compatibles to one between subsets of compatibles. The use of the extended erasure rules can prune the directed tree graph effectively to find a minimum form of a given ISSM. Furthermore, by utilizing the concept of maximal incompatible (MI) we can determine a lower bound for the state number of the minimum form of a given ISSM, and also effectively control the initial steps in generating the directed tree graph. View full abstract»

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  • An Alternative to the Distributed Pipeline

    Publication Year: 1980 , Page(s): 736 - 737
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    An alternative multiple processor organization to the distributed pipeline (DP) [1] is presented. It is shown that the proposed organization is superior to the DP in every respect. View full abstract»

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  • Asymptotically Optimal Circuit for a Storage Access Function

    Publication Year: 1980 , Page(s): 737 - 738
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    Let gk:{0,1}n+k → {0,1}, where n = 2k, be the binary function defined by gk(a1,···, ak, X0,···, xn-1) = x(a) where (a) is the natural number with binary representation a1,···, ak. This function models the reading operation in a random-access storage. In [1] Paul proved a 2n lower bound to the combinational complexity of gk. This correspondence derives a realization for gk in a circuit with 2n + 0(√n) gates and a depth asymptotic to k. View full abstract»

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  • Convolution Computer

    Publication Year: 1980 , Page(s): 738 - 740
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    A special purpose computer is described to evaluate the discrete convolution of two sequences of numbers. This computer abandons the traditional model of convolution as a series of inner products which, for input sequences of length n, requires n multipliers and (n − 1) adders to complete a convolution calculation in (2n − 1) time steps. Instead, it is shown that by reorganizing the algorithm, n interconnected processing units are able to evaluate a convolution in n time steps. Each processing unit consists of a multiplier, an adder, and the necessary buffers. In addition to providing increased throughput, the proposed organization results in a highly modular structure with a well defined interconnection pattern. View full abstract»

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  • Negabinary A/D Conversion

    Publication Year: 1980 , Page(s): 740 - 741
    Cited by:  Papers (1)
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    It is shown that A/D conversion to base –2 may be achieved by making minor modifications to a conventional A/D converter. View full abstract»

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  • Test Sets for Combinational Logic—The Edge-Tracing Approach

    Publication Year: 1980 , Page(s): 741 - 746
    Cited by:  Papers (1)
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    A method for fault analysis of multilevel combinational logic circuits with single stuck-at-faults is described. It determines the sensitizing input combinations (separating edges) from the output function and then traces their paths from the output toward the inputs. The handling of multiple path sensitization in this approach is much simpler than in other path-tracing techniques. Subscripting of variables is not needed and dead-ending (as encountered in the D-algorithm) cannot occur. View full abstract»

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  • Minimally Testable Reed-Muller Canonical Forms

    Publication Year: 1980 , Page(s): 746 - 750
    Cited by:  Papers (2)
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    Arbitrary switching function realizations based upon Reed- Muller canonical (RMC) expansions have been shown to possess many of the desirable properties of easily testable networks. While realizations based upon each of the 2n possible RMC expansions of a given switching function can be tested for permanent stuck-at-0 and stuck-at-1 faults with a small set of input vectors, certain expansions lead to an even smaller test set because of the resulting network topology. In particular, the selection of an RMC expansion that has a minimal number of literals appearing in an even number of product terms will give rise to switching function realizations requiring still fewer tests. This correspondence presents a solution to the problem of selecting the RMC expansion of a given switching function possessing the smallest test set. View full abstract»

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  • Composite Spectra and the Analysis of Switching Circuits

    Publication Year: 1980 , Page(s): 750 - 753
    Cited by:  Papers (8)
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    A method is given for the evaluation of the Rademacher–Walsh spectra of the Boolean sum, product, and EXCLUSIVE-OR of two functions without reintroducing the Rademacher–Walsh transform. The results are derived using a general coding scheme and depend heavily upon the use of a dyadic convolution operation. View full abstract»

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  • Conditional-Sum Early Completion Adder Logic

    Publication Year: 1980 , Page(s): 753 - 756
    Cited by:  Papers (4)
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    A high-speed parallel adder of digitally represented numbers called the conditional-sum early completion adder (CSCA) will be described. The CSCA design is based on the computation of "conditional" sums, carries, and column completion detection logic. View full abstract»

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  • Comments on "A Design of a Fast Cellular Associative Memory for Ordered Retrieval"

    Publication Year: 1980 , Page(s): 756 - 757
    Cited by:  Papers (1)
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    In the above paper1the authors presented (with a reference to an earlier thesis [9] inaccessible to me) a cellular array implementing the following basic searches: equality searches, similarity searches, threshold searches, and extremum searches. View full abstract»

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  • Authors' Reply2

    Publication Year: 1980 , Page(s): 757
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    The idea on the design of cellular associative memories for ordered retrievals had occurred to one of us (Ramamoorthy) around 1970 when he was a consultant to Texas Instruments Incorporated. Subsequently, at his suggestion, the second author (Turner) at the University of Texas, Austin, explored and designed the system. The basic idea was also communicated to Dr. W. Litzler and Mr. Wes Wester of Texas Instruments and the thesis committee of Mr. Turner [4] around the same time. The second author's thesis [4] which was submitted in August 1972 and is available from the Library of the University of Texas at Austin, contains the basic designs and algorithms [4, pp. 14, 21, 32, 46] described in the paper. In 1975, the third author (Wah) improved and applied all the algorithms for associative searches based on database machine design principle. The current design also focuses on the use of associative memory for multiple response resolution. View full abstract»

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  • A Remark on the Nonminimality of Certain Multiple Fault Detection Algorithms

    Publication Year: 1980 , Page(s): 757 - 759
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    Poage has constructed a complex fault detection algorithm which generates a complete and minimal test set of all multiple stuck-at faults of a given combinational network. Several authors have derived from his method fast and simple multiple fault detection algorithms, which are claimed to generate complete test sets with a "near-minimal" or "near-optimal" number of tests. We show that the algorithms by Bossen and Hong and the algorithm by Yang and Yau may generate test sets with an exponential number of tests (relative to the number of inputs) where a linear number of tests is sufficient for a complete multiple fault detection test set. View full abstract»

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  • Author's reply2

    Publication Year: 1980 , Page(s): 759
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  • Correction to "Properties of the Multidimensional Generalized Discrete Fourier Transform"

    Publication Year: 1980 , Page(s): 759
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    The following typographical errors should be noted in the above paper.1 View full abstract»

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  • Call for Papers

    Publication Year: 1980 , Page(s): 759
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    Freely Available from IEEE
  • IEEE Computer Society Publications

    Publication Year: 1980 , Page(s): 759
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    Freely Available from IEEE
  • Advance Announcement... Tutorial Week 80

    Publication Year: 1980 , Page(s): 759
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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
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e-mail: pmo@computer.org