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IEEE Transactions on Computers

Issue 7 • Date July 1980

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Displaying Results 1 - 23 of 23
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1980, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1980, Page(s): c2
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  • On the Complexity of Sorting in Magnetic Bubble Memory Systems

    Publication Year: 1980, Page(s):553 - 563
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2652 KB)

    In this paper the problem of sorting in various models of magnetic bubble memory systems is studied. Three basic parameters are of interest, namely, the number of steps to sort, the number of switches required, and the number of control states necessary for the switches. Several sorting algorithms are proposed with respective running times essentially n2, n/2, 1/2 n log2 n, 7/2 n, n log... View full abstract»

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  • The Parallel Recognition of Classes of Graphs

    Publication Year: 1980, Page(s):563 - 570
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3554 KB)

    Parallel cellular algorithms for recognizing adjacency and incidence matrices of several classes of graphs are given. These classes include cubic graphs, complete graphs, connected graphs, and trees. View full abstract»

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  • An Optimal Worst Case Algorithm for Reporting Intersections of Rectangles

    Publication Year: 1980, Page(s):571 - 577
    Cited by:  Papers (37)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2621 KB)

    In this paper we investigate the problem of reporting all intersecting pairs in a set of n rectilinearly oriented rectangles in the plane. This problem arises in applications such as design rule checking of very large-scale integrated (VLSI) circuits and architectural databases. We describe an algorithm that solves this problem in worst case time proportional to n lg n + k, where k is the number o... View full abstract»

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  • A Dynamically Microprogrammable Computer with Low-Level Parallelism

    Publication Year: 1980, Page(s):577 - 595
    Cited by:  Papers (3)  |  Patents (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (9653 KB)

    A new microprogrammable computer with low-level parallelism was built and has been utilized as a research vehicle for solving different classes of research-oriented applications such as real-time processings on static/dynamic images, pictures and signals, and emulations of both existing and virtual machines including high (intermediate) level language machines. The design goal of the machine was t... View full abstract»

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  • Packet Broadcast Networks—A Performance Analysis of the R-ALOHA Protocol

    Publication Year: 1980, Page(s):596 - 603
    Cited by:  Papers (85)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2386 KB)

    In packet broadcast networks, users are interconnected via a broadcast channel. The key problem is multiple access of the shared broadcast channel. The performance of the R-ALOHA protocol for multiple access is studied in this paper. Two user models with Poisson message arrivals are analyzed; each message consists of a group of packets with a general probability distribution for group size. In the... View full abstract»

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  • Complex Number Arithmetic with Odd- Valued Logic

    Publication Year: 1980, Page(s):604 - 611
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3599 KB)

    Digital signal processing such as discrete Fourier transform requires complex number arithmetic. Number-theoretical properties favor odd-radix systems for simple implementation of complex number operations. An array ternary complex multiplier is presented and compared to other complex multipliers. As an illustration, a perfectly balanced ternary system is implemented by means of current-mode thres... View full abstract»

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  • Optimization of Memory Hierarchies in Multiprogrammed Computer Systems With Fixed Cost Constraint

    Publication Year: 1980, Page(s):611 - 618
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3557 KB)

    This paper presents, using queuing theory and optimization techniques, an approach for estimating the optimal capacities and speeds of the memory levels in a memory hierarchy operating in the multiprogrammed environment. Optimality is defined with respect to mean system response time under a fixed cost constraint. It is assumed that the number of levels in the hierarchy as well as the capacity of ... View full abstract»

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  • Fast Sorting Algorithms on Uniform Ladders (Multiple Shift-Register Loops)

    Publication Year: 1980, Page(s):618 - 631
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4657 KB)

    This paper presents two sorting algorithms on the uniform ladder (a new storage device based on charged coupled devices, or magnetic bubbles implementation, proposed by Chen et al.). It is assumed that control and comparison timings are negligible when compared to the relatively slow bubble movements. The first algorithm (Algorithm 1) enables the sorting process on a single ladder to be completely... View full abstract»

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  • A Computation Model of Parallel Solution of Linear Equations

    Publication Year: 1980, Page(s):632 - 638
    Cited by:  Papers (26)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2372 KB)

    The solution process of Ax = b is modeled by an acyclic directed graph in which the nodes represent the arithmetic operations applied to the elements of A, and the arcs represent the precedence relations that exist among the operations in the solution process. Operations that can be done in parallel are identified in the model and the absolute minimum completion time and lower bounds on the minimu... View full abstract»

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  • Theory and Design of Mixed-Mode Sequential Machines

    Publication Year: 1980, Page(s):639 - 648
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3019 KB)

    A mixed mode sequential machine (MSM) is defined as a representation in which both synchronous (clocked) and asynchronous (unclocked) state transitions are allowed. The intent of the representation is to allow designers to consider both types of transitions in a single structure, thereby promoting the use of LSI devices such as ROM's or PLA's to resolve the realization question. The approach is th... View full abstract»

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  • Minimal Redundant Logic for High Reliability and Irredundant Testability

    Publication Year: 1980, Page(s):648 - 656
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3474 KB)

    The procedures introduced in this paper convert redundant circuits into irredundant circuits for testing purposes. In a redundant circuit, there are redundant connections which contribute no unique l's or 0's to the output of the circuit. These redundant connections are contained in the circuit for specific purposes, such as hazard protection, integrated circuit standardization, structural purpose... View full abstract»

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  • Polylogic Realization of Switching Functions

    Publication Year: 1980, Page(s):657 - 659
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (505 KB)

    The properties of polynomic functions on Rn are reviewed. Such functions are then used to establish a general synthesis procedure for arbitrary multivalued switching functions. The relationship with threshold logic and Boolean logic is also explored. View full abstract»

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  • Some Results Concerning Data Routing in Array Processors

    Publication Year: 1980, Page(s):659 - 662
    Cited by:  Papers (3)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    Some properties of k-dimensional cyclic networks are derived and used to give some algorithmic timings for the transposition of rectangular sets of data in an array processor's memory. General results are produced which can be applied to ICL's distributed array processor (DAP). View full abstract»

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  • Complete Solution of Boolean Equations

    Publication Year: 1980, Page(s):662 - 665
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (717 KB)

    A method is presented for generating a single formula involving arbitrary Boolean parameters, which includes in it each and every possible solution of a system of Boolean equations. An alternate condition equivalent to a known necessary and sufficient condition for solving a system of Boolean equations is given. View full abstract»

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  • Separating and Completely Separating Systems and Linear Codes

    Publication Year: 1980, Page(s):665 - 668
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (919 KB)

    In this correspondence, we present some more properties of separating systems (SS) and completely separating systems (CSS) from coding theory framework. First we derive the necessary and sufficient conditions for a set of vectors to be a SS or CSS. Then we show that in the case of linear codes, the necessary and sufficient conditions required for (1, 1) CSS are similar to that of (2, 1) SS and by ... View full abstract»

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  • Testing by Feedback Shift Register

    Publication Year: 1980, Page(s):668 - 673
    Cited by:  Papers (38)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1225 KB)

    A compact testing method called feedback shift register testing (FSR testing) is presented and its properties, concerning detection and diagnosis, are given. The new notion of distinction potential is introduced. The proposed method is shown to have the maximum resolution and the maximum distinction potential that can be found for an m-bit signature. View full abstract»

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  • Detection of Single Intermittent Faults in Sequential Circuits

    Publication Year: 1980, Page(s):673 - 678
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1167 KB)

    Testing for intermittent faults in digital circuits has been given significant attention in the past few years. However, very little theoretical work was done regarding their detection in sequential circuits. View full abstract»

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  • 254: Proceedings: COMPCON 79 Fall "Using Microprocessors—Extending our Reach"

    Publication Year: 1980, Page(s): 678-a
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  • Proceedings of the Conference on Specifications of Reliable Software

    Publication Year: 1980, Page(s): 678-b
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    Freely Available from IEEE
  • IEEE Computer Society Publications

    Publication Year: 1980, Page(s): 678
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    Freely Available from IEEE
  • Compcon 80 Fall

    Publication Year: 1980, Page(s): 678
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    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org