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IEEE Transactions on Computers

Issue 6 • Date June 1980

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Displaying Results 1 - 25 of 26
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1980, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1980, Page(s): c2
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  • Fault-Tolerant Computing: An Introduction

    Publication Year: 1980, Page(s):417 - 419
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1726 KB)

    THE first Special Issue on Fault-Tolerant Computing was published in this TRANSACTIONS nearly a decade ago [1]. Five other Special Issues devoted to this same topic followed [2]-[6]; this is the seventh in the series. These seven issues contain a representative sample (over 120 papers and correspondences) of the research activities that have taken place in fault-tolerant computing over the past de... View full abstract»

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  • Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories

    Publication Year: 1980, Page(s):419 - 429
    Cited by:  Papers (74)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4272 KB)

    A class of pattern-sensitive faults in semiconductor random-access memories are studied. Efficient test procedures to detect and locate modeled faults are presented. View full abstract»

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  • Test Generation for Microprocessors

    Publication Year: 1980, Page(s):429 - 441
    Cited by:  Papers (222)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4602 KB)

    The goal of this paper is to develop test generation procedures for testing microprocessors in a user environment. Classical fault detection methods based on the gate and flip-flop level or on the state diagram level description of microprocessors are not suitable for test generation. The problem is further compounded by the availability of a large variety of microprocessors which differ widely in... View full abstract»

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  • Syndrome-Testable Design of Combinational Circuits

    Publication Year: 1980, Page(s):442 - 451
    Cited by:  Papers (153)  |  Patents (34)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2668 KB)

    Classical testing of combinational circuits requires a list of the fault-free response of the circuit to the test set. For most practical circuits implemented today the large storage requirement for such a list makes such a test procedure very expensive. Moreover, the computational cost to generate the test set increases exponentially with the circuit size. View full abstract»

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  • Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis

    Publication Year: 1980, Page(s):451 - 460
    Cited by:  Papers (75)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4073 KB)

    In this paper we present a new approach to multiple fault diagnosis in combinational circuits based on an effect-cause analysis. The main vehicle of our approach is the deduction of internal line values in a circuit under test N*. The knowledge of these values allows us to identify fault situations in N* (causes) which are compatible with the applied test and the obtained response (the effect). A ... View full abstract»

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  • Diagnosis Without Repair for Hybrid Fault Situations

    Publication Year: 1980, Page(s):461 - 470
    Cited by:  Papers (40)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2977 KB)

    For a new class of fault situations called hybrid fault situations, we consider the fault diagnosing capabilities of systems which for testing/monitoring purposes can be viewed as being composed of independent units. The classical Preparata, Metze, and Chien model (PMC model) is used to specify the various testing assignments among the units. Hybrid fault situations are described as explicitly bou... View full abstract»

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  • A New Class of Error-Correcting/Detecting Codes for Fault-Tolerant Computer Applications

    Publication Year: 1980, Page(s):471 - 481
    Cited by:  Papers (67)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3111 KB)

    Separable error-correcting/detecting codes are developed that provide protection against combinations of both unidirectional and random errors. Specifically, codes are presented which can both: 1) correct (detect) some t random errors, and 2) detect any number of unidirectional errors which may also contain t or fewer random errors. Necessary and sufficient conditions for the existence of these co... View full abstract»

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  • Recovery and Diagnostics in the Central Control of the AXE Switching System

    Publication Year: 1980, Page(s):482 - 491
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2969 KB)

    AXE is a stored program controlled (SPC) telephone exchange system. Its control system typically comprises 100 000 IC packages with MTBF = 200 h. The application allows the control system to contribute to the system outage with only a few minutes per year. An ordinary telephone technician is able to maintain the system, mainly during normal working hours. View full abstract»

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  • Fault Tolerance of a General Purpose Computer Implemented by Very Large Scale Integration

    Publication Year: 1980, Page(s):492 - 500
    Cited by:  Papers (50)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2873 KB)

    The construction of computer systems containing integrated circuit logic components with very large scale integration (VLSI), that is, many thousands of gates, is inevitable. Such levels of integration have already been achieved in memory components. There are significant problems in using some conventional fault-tolerant techniques in VLSI implementations for general purpose computers; consequent... View full abstract»

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  • Performability Evaluation of the SIFT Computer

    Publication Year: 1980, Page(s):501 - 509
    Cited by:  Papers (47)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3024 KB)

    Performability modeling and evaluation methods are applied to the SIFT computer in the computational environment of an air transport mission. User-visible performance of the "total system" (SIFT plus its environment) is modeled as a random variable taking values in a set of "accomplishment levels." These levels are defined in terms of four attributes of total system behavior: safety, no change in ... View full abstract»

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  • Measures of the Effectiveness of Fault Signature Analysis

    Publication Year: 1980, Page(s):510 - 514
    Cited by:  Papers (136)  |  Patents (44)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1176 KB)

    A linear feedback shift register can be used to compress a serial stream of test result data. The compressed erroneous bit stream caused by a fault is said to form the "signature" of the fault. Since the bit stream is compressed, however, it is possible for an erroneous bit stream and the correct one to result in the same signature. View full abstract»

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  • Minimal Detecting Transition Sequences: Application to Random Testing

    Publication Year: 1980, Page(s):514 - 518
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1193 KB)

    This paper presents the new notion of minimal detecting transition sequence (MDTS). A detectable fault f in a circuit C is detected by any MDTS in a set Df called detection set associated with f. From a prescribed set of faults, we obtain a list of detection sets. This list of detection sets is calculated once for all, for a given circuit C. Once this list bas been obtained for a circuit, it may b... View full abstract»

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  • Multiple Fault Detection in Programmable Logic Arrays

    Publication Year: 1980, Page(s):518 - 522
    Cited by:  Papers (47)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1153 KB)

    The increasing recognition of PLA's as efficient and viable modules for such purposes as microprogramming and design of sequential controllers has led to a growing interest in the development of optimum fault detection test sets for these modules. It is now well known that a fault type which is unique to PLA's is the class of contact faults. A single contact fault is the spurious presence or absen... View full abstract»

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  • Detection and Location of Input and Feedback Bridging Faults Among Input and Output Lines

    Publication Year: 1980, Page(s):523 - 527
    Cited by:  Papers (32)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1083 KB)

    The study of short circuits between conducting paths (bridging faults) has become increasingly important. Yet very little work has been done in this area. In this paper, conditions for feedback bridging (short circuit) faults to generate oscillation and asynchronous behavior are given for short circuits among input lines and the primary output. The lower and upper bounds on the number of tests for... View full abstract»

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  • Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability

    Publication Year: 1980, Page(s):527 - 531
    Cited by:  Papers (241)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1202 KB)

    At the end of an IC production line, integrated circuits are generally submitted to three kinds of tests: 1) parametric tests to check electrical characteristics (voltage, current, power consumption), 2) dynamic tests to check response times under nominal operating conditions, and 3) functional tests to check its logical behavior. View full abstract»

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  • Design of Self-Checking MOS-LSI Circuits: Application to a Four-Bit Microprocessor

    Publication Year: 1980, Page(s):532 - 537
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1262 KB)

    Self-checking approaches developed so far deal with a gate level representation of logical circuits. They do not account for constraints which may result from an implementation by integrated circuits. This paper is concerned with such practical problems and their respective significance. View full abstract»

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  • Multivalued I2L Circuits for TSC Checkers

    Publication Year: 1980, Page(s):537 - 540
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (747 KB)

    We present a TSC multivalued I2L comparator which uses multivalued current inputs and two binary voltage outputs. This circuit is self-testing and fault-secure for single faults (either "stuck-at" or "skew" faults). It is the basic circuit to realize TSC checkers for nonseparable or separable codes. The schemes are simpler than the designs of the TSC combinational checkers. View full abstract»

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  • Design of Self-Diagnosable Multiprocessor Systems with Concurrent Computation and Diagnosis

    Publication Year: 1980, Page(s):540 - 546
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1294 KB)

    The advent of microprocessors as low-cost general- purpose computing elements has made feasible the implementation of multiprocessor systems containing a large number of cooperating modules. When the number of modules in the system is large it is unlikely that all of them are busy with computation at all times. Therefore, it may be possible to utilize this "slack" by having the nonbusy modules per... View full abstract»

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  • A Recovery Cache for the PDP-11

    Publication Year: 1980, Page(s):546 - 549
    Cited by:  Papers (21)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1000 KB)

    Backward error recovery is an integral part of the recovery block scheme that has been advanced as a method for providing tolerance against faults in software; the recovery cache has been proposed as a mechanism for providing this error recovery capability. This correspondence describes a recovery cache that has been built for the PDP-11 family of machines. This recovery cache has been designed to... View full abstract»

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  • 254: Proceedings: COMPCON 79 Fall "Using Microprocessors—Extending our Reach"

    Publication Year: 1980, Page(s): 549-a
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    Freely Available from IEEE
  • Proceedings of the Conference on Specifications of Reliable Software

    Publication Year: 1980, Page(s): 549-b
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    Freely Available from IEEE
  • 249 4th International Conference on Software Engineering

    Publication Year: 1980, Page(s): 549-c
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    Freely Available from IEEE
  • IEEE Computer Society Publications

    Publication Year: 1980, Page(s): 549
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    Freely Available from IEEE

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org