IEEE Transactions on Computers

Issue 5 • May 1980

Filter Results

Displaying Results 1 - 17 of 17
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1980, Page(s): c1
    Request permission for commercial reuse | PDF file iconPDF (421 KB)
    Freely Available from IEEE
  • IEEE Computer Society

    Publication Year: 1980, Page(s): c2
    Request permission for commercial reuse | PDF file iconPDF (217 KB)
    Freely Available from IEEE
  • An Improved Lower Bound on Polynomial Multiplication

    Publication Year: 1980, Page(s):337 - 340
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1825 KB)

    We prove an asymptotic lower bound of 3.52n nonscalar multiplications for (degree n – 1 by degree n – 1) polynomial multiplication in a model which allows only integers as scalars. Index Terms-Algebraic complexity, lower bound, polynomial multiplication. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Arithmetic for Ultra-High-Speed Tomography

    Publication Year: 1980, Page(s):341 - 353
    Cited by:  Papers (19)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4635 KB)

    The first of a new generation of high performance X-ray computed tomographic (CT) machines, the Dynamic Spatial Reconstructor, imposes a requirement for digital signal processing rates which are 3–4 orders of magnitude greater than the capability of current X-ray computed tomography processors. To solve the large-scale computational problems for this and similar CT units which are currently ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On Block-Parallel Methods for Solving Linear Equations

    Publication Year: 1980, Page(s):354 - 359
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2048 KB)

    An MIMD-type parallel-processing system was introduced recently. Using an extended PL/I notation, algorithms for the Gauss-Seidel method and for back substitution are written for this system. Block execution is shown to result in higher speedups. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Processor Interconnection Strategies

    Publication Year: 1980, Page(s):360 - 371
    Cited by:  Papers (26)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2956 KB)

    In this paper, we describe four families of topologies for interconnecting many identical processors into a computer network. Each family extends to arbitrarily many processors while keeping the number of neighbors of any one processor fixed. These families are investigated with respect to bus load, routing algorithms, and the relation between the average interprocessor distance and the size of th... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Queueing Analysis of Global Locking Synchronization Schemes for Multicopy Databases

    Publication Year: 1980, Page(s):371 - 384
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5032 KB)

    Locking is a simple scheme to synchronize multiple updates in a multicopy distributed database system. Various schemes were proposed before to maintain the consistency of the distributed database. But these schemes were compared to each other mostly on heuristic base. In this paper, three analytic queueing models for the Network Semaphore scheme, Hopping Permit scheme, and Adaptive Hopping Permit ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Simulation of a Class of Ring-Structured Networks

    Publication Year: 1980, Page(s):385 - 392
    Cited by:  Papers (29)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2443 KB)

    This paper presents a new modular loop/ring architecture combining advantages of several earlier centralized and decentralized ring-structured loop networks while remaining simple. This is accomplished by introducing two major innovations: first, use of a separate control loop for control messages flowing between nodes and a loop controller; second, dynamically implementing partitionable segments ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Parallel Compressors

    Publication Year: 1980, Page(s):393 - 398
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1065 KB)

    A subclass of generalized parallel counters, called parallel compressors, is introduced in this correspondence. Under present-day packaging technology, parallel compressors with their higher compression ratio and fewer input/output pins are more efficient in multiple operand addition and multiplication than parallel counters. Cost and time bounds are obtained for schemes using parallel compressors... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-Speed M-Sequence Generators

    Publication Year: 1980, Page(s):398 - 400
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (603 KB)

    The generation of high-speed maximal length "M"-sequences is at the heart of many diverse techniques, notably code-division multiple access communications systems, or spectrum spreading, and precise ranging disciplines. This paper develops a rich family of M-sequences whose upper speed bound is set by the fastest shift register stage available in the technology under consideration and not by logic... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders

    Publication Year: 1980, Page(s):400 - 403
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (803 KB)

    Parallel counters are multiple input circuits that count the number of their inputs that are in a given state. In this correspondence, the implementation of pipelined binary parallel counters with networks of latched quaternary threshold logic full adders is described and compared with the implementation using networks of latched binary full adders. Since each signal variable in quaternary logic m... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A High Data-Rate Digital Output Correlator Design

    Publication Year: 1980, Page(s):403 - 405
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (797 KB)

    A high data-rate digital output correlator integrated circuit design which uses new synchronous sequential quaternary threshold logic gates is proposed and compared to the all-binary equivalent realization of this function. Substantial integrated circuit device count and die area savings are projected for the multiple valued logic realization. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Sequential Machines Having Quasi-Stable States

    Publication Year: 1980, Page(s):405 - 408
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (761 KB)

    This correspondence investigates a model of description for sequential systems having state-transitions among any number of stable states, quasi-stable states, and unstable states. The quasi-stable states are typically seen in the so-called astable and monostable multivibrators in pulse circuits. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Autocorrelation Function of Sequential M-Bit Words Taken from an N-Bit Shift Register (PN) Sequence

    Publication Year: 1980, Page(s):408 - 410
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (530 KB)

    A closed-form expression is obtained for the autocorrelation function of sequential M-bit, base α digital words formed by serial bits of a single binary PN sequence of length L = 2N − 1. Plots are presented for several values of M and N, showing detailed behavior and limiting curves for the binary case (α= 2). View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection

    Publication Year: 1980, Page(s):410 - 416
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1092 KB)

    Intermittent faults in combinational circuits may appear and disappear randomly; hence, their detection requires many repeated applications of test vectors. Since testing reduces the time available for computation, it is necessary to efficiently minimize the time required for a test, while still achieving a high degree of fault detection. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • IEEE Computer Society Publications

    Publication Year: 1980, Page(s): 416
    Request permission for commercial reuse | PDF file iconPDF (157 KB)
    Freely Available from IEEE
  • call for papers

    Publication Year: 1980, Page(s): 416
    Request permission for commercial reuse | PDF file iconPDF (1230 KB)
    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org