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Computers, IEEE Transactions on

Issue 3 • Date March 1980

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Displaying Results 1 - 12 of 12
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1980 , Page(s): c1
    Save to Project icon | Request Permissions | PDF file iconPDF (313 KB)  
    Freely Available from IEEE
  • IEEE Computer Society

    Publication Year: 1980 , Page(s): c2
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    Freely Available from IEEE
  • Notes on Shuffle/Exchange-Type Switching Networks

    Publication Year: 1980 , Page(s): 213 - 222
    Cited by:  Papers (75)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2707 KB)  

    In this paper a number of properties of Shuffle/Exchange networks are analyzed. A set of algebraic tools is developed and is used to prove that Lawrie's inverse Omega network, Pease's indirect binary n-cube array, and a network related to the 3-stage rearrangeable switching network studied by Clos and Beneš have identical switching capabilities. The approach used leads to a number of insights on the structure of the fast Fourier transform (FFT) algorithm. The inherent permuting power, or "universality," of the networks when used iteratively is then probed, leading to some nonintuitive results which have implications on the optimal control of Shuffle/Exchange-type networks for realizing permutations and broadcast connections. View full abstract»

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  • Functional Level Primitives in Test Generation

    Publication Year: 1980 , Page(s): 223 - 235
    Cited by:  Papers (37)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3258 KB)  

    This paper deals with the use and development of high-level (functional) primitive logic elements for use in a system which automatically generates tests for complex sequential circuits. The concept of solution sequences to test problems for primitive elements is introduced and a functional language used to describe solution sequences is presented. Functional test generation models for two basic elements, a shift register and a counter, are derived, including procedures for implication, D-drive and line justification. Primitive algorithms which generate single as well as multivector (sequences) solutions to D-drive and line justification problems are presented. View full abstract»

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  • An Experimental Delay Test Generator for LSI Logic

    Publication Year: 1980 , Page(s): 235 - 248
    Cited by:  Papers (111)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4691 KB)  

    Delay testing is a test procedure to verify the timing performance of manufactured logic networks. When a level-sensitive scan design (LSSD) discipline is used, all networks are combinational. Appropriate test patterns are selected on the basis of certain theoretical criteria. These criteria are embodied in an experimental test generation program. The program has successfully produced sets of delay tests for large logic networks. The average coverage achieved by these tests faDs within 95.8 percent to 99.9 percent of optimal. View full abstract»

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  • Testing Memories for Single-Cell Pattern-Sensitive Faults

    Publication Year: 1980 , Page(s): 249 - 254
    Cited by:  Papers (55)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1346 KB)  

    The design of minimum-length test sequences for pattern sensitivity in random-access memory (RAM) arrays is examined. The single pattern-sensitive fault (SPSF) model is used in which operations addressed to at most one memory cell are allowed to be faulty at any time. The influence of an SPSF affecting cell Ci is restricted to a fixed set of cells called the neighborhood of Ci. A new method is presented for efficiently generating the sequence of writes required in an SPSF test. This method yields optimal sequences for a useful class of neighborhoods called tiling neighborhoods. It is observed that RAM neighborhoods can be interpreted as polyominoes. A general procedure is given for constructing an SPSF test containing the minimum number of writes but a nonminimum number of reads. The difficult problem of minimizing the number of reads in an SPSF test is investigated for the 2-cell memory M2. A test of length 36 for M2 is derived which is optimal under certain reasonable restrictions. It is demonstrated that minimum-length SPSF tests can be inherently asymmetric. View full abstract»

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  • A Hardware Redundancy Reconfiguration Scheme for Tolerating Multiple Module Failures

    Publication Year: 1980 , Page(s): 254 - 258
    Cited by:  Papers (6)  |  Patents (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1026 KB)  

    This paper deals with a method for designing a digital system which will remain operational in spite of the failure of some of its components. A scheme and its realization are presented for automatically reconfiguring a 5MR (five modular redundancy system or 5-input majority voting system) into a triple modular redundancy (TMR) system under a single or double module failures. The scheme can tolerate a double fault followed by a single fault which can neither be tolerated by a 5MR nor by a hybrid redundancy system with a TMR core. It uses no spare units and the circuit realization is relatively simple. The modular structure of the logic design for the proposed scheme should make the testing of the system easier. The scheme can be used in both binary and multivalued systems. View full abstract»

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  • A Digital Quarter Square Multiplier

    Publication Year: 1980 , Page(s): 258 - 261
    Cited by:  Papers (5)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (635 KB)  

    An application of the quarter square multiplication technique used in analog computing is proposed for digital multiplication. Significant savings in storage requirements for ROM- implemented product tables are demonstrated. A two's complement multiplication circuit utilizing the digital quarter square technique is presented. View full abstract»

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  • A New Approach to the Evaluation of the Reliability of Digital Systems

    Publication Year: 1980 , Page(s): 261 - 267
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1053 KB)  

    Signal reliability, as a measure of digital systems' reliability, has not been used until recently due to lack of efficient evaluation methods. A new approach to the evaluation of signal reliability is presented in this work. A reliability transfer function of digital systems is defined and a method for its evaluation is presented. This approach provides a new insight into the problem of digital system reliability. Furthermore, it simplifies signal reliability calculations and can easily be mechanized. View full abstract»

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  • Call for Papers

    Publication Year: 1980 , Page(s): 267
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    Freely Available from IEEE
  • IEEE Computer Society Publications

    Publication Year: 1980 , Page(s): 267
    Save to Project icon | Request Permissions | PDF file iconPDF (152 KB)  
    Freely Available from IEEE
  • Call for Papers

    Publication Year: 1980 , Page(s): 267
    Save to Project icon | Request Permissions | PDF file iconPDF (1304 KB)  
    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org