IEEE Transactions on Computers

Issue 2 • Feb. 1980

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  • IEEE Transactions on Computers

    Publication Year: 1980, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1980, Page(s): c2
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  • Table of contents

    Publication Year: 1980, Page(s): 65
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  • Foreword

    Publication Year: 1980, Page(s):66 - 67
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  • A Cordic Arithmetic Processor Chip

    Publication Year: 1980, Page(s):68 - 79
    Cited by:  Papers (116)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5188 KB)

    A monolithic processor computes products, quotients, and several common transcendental functions. The algorithms are based on the well-known principles of "CORDIC," but recourse to a subtle novel corollary results in a scale factor of unity. Compared to older machines, the overhead burden is significantly reduced. Also, expansion of the functional repertoire beyond the circular domain, i.e., addit... View full abstract»

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  • Dedicated LSI for a Microprocessor-Controlled Hand-Carried OCR System

    Publication Year: 1980, Page(s):79 - 88
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6270 KB)

    The binary picture processing and recognizing stages of an optical character recognition (OCR) system have been designed using both flexibility of available microprocessors and speed of peripheral custom-designed integrated circuits. A dedicated large-scale integrated (LSI) processor performs edge detection and thinning of a 32 × 24 digitized one-piece pattern. The output signal–a set o... View full abstract»

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  • The Development of a Bubble Memory Controller for Low-Cost File Use

    Publication Year: 1980, Page(s):89 - 96
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4910 KB)

    The bubble memory has several features such as low-cost low-power consumption, small physical size, high reliability, and non- volatility, which make it suitable for low-cost microcomputer files. View full abstract»

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  • An NMOS Microprocessor for Analog Signal Processing

    Publication Year: 1980, Page(s):97 - 102
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3522 KB)

    A special purpose microprocessor for real time processing of analog signals is described. Design and implementation of architecture allowing a user programmable and erasable read only memory (EPROM), a 25 bit digital processor and a 9 bit analog acquisition system on the same substrate is discussed. The relationship between the device's resources and specific signal processing building blocks is d... View full abstract»

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  • An NMOS Microcomputer Peripheral Interface Unit Incorporating an Analog-to-Digital Converter

    Publication Year: 1980, Page(s):102 - 107
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4688 KB)

    A peripheral interface unit for a microcomputer control system fabricated by a standard n-channel silicon-gate enhancement/ depletion MOS process is described. This unit can accept analog and digital inputs, generate pulse outputs, and multiply. The analog input capability is made possible by an on-chip A/D converter using a constant slope approach with an external capacitor. This converter can pe... View full abstract»

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  • Design Considerations for Single-Chip Computers of the Future

    Publication Year: 1980, Page(s):108 - 116
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4416 KB)

    In the mid 1980's it will be possible to put a million devices (transistors or active MOS gate electrodes) onto a single silicon chip. General trends in the evolution of silicon integrated circuits are reviewed and design constraints for emerging VLSI circuits are analyzed. Desirable architectural features in modern computers are then discussed and consequences for an implementation with large-sca... View full abstract»

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  • An LSI Implementation of an Intelligent CRC Computer and Programmable Character Comparator

    Publication Year: 1980, Page(s):116 - 124
    Cited by:  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3574 KB)

    Manufacturers of MOS microprocessors have been expanding their product families to include function or task oriented LSI peripheral controllers. In the data communications area, circuits such as universal synchronous/asynchronous receiver/transmitters, bit oriented data link controllers, and multiprotocol handlers have greatly simplified systems design. View full abstract»

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  • Acceptable Testing of VLSI Components Which Contain Error Correctors

    Publication Year: 1980, Page(s):125 - 134
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3287 KB)

    If a VLSI chip is partitioned into functional units (FU's) and redundant FU's are added, error correcting codes may be employed to increase the yield and/or reliability of the chip. Acceptable testing is defined to be testing the chip with the error corrector functioning, thus obtaining the maximum increase in yield afforded by the error correction. The acceptable testing theorem shows that the us... View full abstract»

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  • A High-Speed Microprogrammable Digital Signal Processor Employing Distributed Arithmetic

    Publication Year: 1980, Page(s):134 - 144
    Cited by:  Papers (7)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3942 KB)

    This paper describes a general-purpose digital-signal processor which is constructed with 4 bit bipolar microprocessor slices. The signal processor is microprogrammable and contains special features which allow it to employ distributed arithmetic. Hence, the processor can achieve high sampling rates without using a hardware multiplier unit. The processor's architecture is presented and its micro-o... View full abstract»

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  • Optimal Interconnections in the Design of Microprocessors and Digital Systems

    Publication Year: 1980, Page(s):145 - 149
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3259 KB)

    This paper recasts the multiple data path assignment problem solved by Torng and Wilhelm by the dynamic programming method [1] into a minimal covering problem following a switching theoretic approach. The concept of bus compatibility for the data transfers is used to obtain the various ways of interconnecting the circuit modules with the minimum number of buses that allow concurrent data transfers... View full abstract»

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  • Modular Minicomputers Using Microprocessors

    Publication Year: 1980, Page(s):149 - 160
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4991 KB)

    This paper presents the design and breadboard implementation of an experimental multiprocessor (mP) whose objectives were 1) to provide modularity of performance over the range of 0.2 million instructions/s (mips) to about 3 mips and 2) to optimize cost-performance over this selected range by exploiting the high technology of microprocessors and RAM's. View full abstract»

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  • Performance of Cooperative Loosely Coupled Microprocessor Architectures in an Interactive Data Base Task

    Publication Year: 1980, Page(s):161 - 180
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4847 KB)

    Continuing technological advances in single-chip intelligence and storage cell density, and in bulk store performance provide increasing opportunities to construct multiple microprocessor systems. The objective of this experimental study was to explore the performance of selected system architectures in a manner sufficiently detailed, quantitative and realistic to 1) contribute to our understandin... View full abstract»

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  • Move Architecture in Digital Controllers

    Publication Year: 1980, Page(s):180 - 190
    Cited by:  Papers (25)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2989 KB)

    The conditional MOVE processor (CMOVE) has been proposed for replacement of logic table driven sequencers like traffic light controllers and microcomputer I/O processors, in order to take better advantage of hardware-software tradeoffs. Herein the architecture of the CMOVE processor is sketched, and its application to traditional numerical control problems is studied. View full abstract»

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  • High Density Integrated Computing Circuitry with Multiple Valued Logic

    Publication Year: 1980, Page(s):191 - 195
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (938 KB)

    It is well known that multiple valued logic can theoretically provide a greater logical packing density than binary logic. In this correspondence, a useful quaternary logic arithmetic circuit is discussed in its combinational and synchronous sequential forms. The results of applying this circuit in proposed implementations of digital parallel counters are then compared to all-binary designs. A sig... View full abstract»

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  • Design and Realization of a Two-Level 64K Byte CCD Memory System for Microcomputer Applications

    Publication Year: 1980, Page(s):195 - 199
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2066 KB)

    Charge coupled device (CCD) memory technology offers potential economic advantages over semiconductor random-access memory technology. However, the limitations incurred by the serial nature of CCD's have previously restricted their application to computer mainframe memories. The 64 kbyte CCD memory system described in this paper demonstrates the feasibility of CCD memory technology for moderate si... View full abstract»

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  • Digital Multiplexing of Analog Data in a Microprocessor Controlled Data Acquisition System

    Publication Year: 1980, Page(s):200 - 202
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    An analog data acquisition system typically consists of an analog multiplexor followed by an analog to digital (A/D) converter. An alternative configuration uses multiple comparators (one per input) followed by a digital multiplexor. If the control functions for A/D conversion are incorporated into a microprocessor, several potentially interesting data acquisition and conversion strategies are ava... View full abstract»

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  • Design of Dependent-Failure-Tolerant Microcomputer System Using Triple-Modular Redundancy

    Publication Year: 1980, Page(s):202 - 206
    Cited by:  Papers (15)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (913 KB)

    Microcomputer system reliability using triple-modular redundancy (TMR) is discussed when failures exist not only in any single module but also in any two or three modules at a time. The optimal time interval is calculated by which the system will even be resynchronized periodically so that additional transient failures can be tolerated. It is shown that in spite of the optimal resynchronization, t... View full abstract»

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  • Microprocessor Utilization in Satellite-Born Packet Switching

    Publication Year: 1980, Page(s):206 - 208
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    This correspondence deals with the application of a bit slice microprocessor to a satellite born packet switch. A system architecture for accomplishing this task is proposed, and the performance of the packet switch is evaluated by obtaining an upper bound on the system throughput. View full abstract»

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  • MTEC: A Microprocessor System for Astronomical Telescope and Instrument Control

    Publication Year: 1980, Page(s):208 - 211
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1964 KB)

    A flexible and modular control system for astronomical telescopes and their associated observational instruments is implemented using an eight-bit microprocessor, and the various design features of a compact single board computer are discussed. A simple message protocol and system of UART serial links is used to achieve modularity and expandability of such a control system employing a central mini... View full abstract»

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  • Call for Papers

    Publication Year: 1980, Page(s): 211
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  • IEEE Computer Society Publications

    Publication Year: 1980, Page(s): 211
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    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org