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Computers, IEEE Transactions on

Issue 11 • Date Nov. 1980

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Displaying Results 1 - 18 of 18
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1980 , Page(s): c1
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    Freely Available from IEEE
  • IEEE Computer Society

    Publication Year: 1980 , Page(s): c2
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    Freely Available from IEEE
  • Magnetic Bubble Memory Architectures for Supporting Associative Searching of Relational Databases

    Publication Year: 1980 , Page(s): 957 - 970
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3983 KB)  

    A memory organized around a major/minor loop magnetic bubble storage unit contains database information in relational form. An external marker memory, consisting of an M-bit shift register or an M X 1 RAM, provides, in conjunction with an assumed processing element, an associative search capability. Each bit accumulates search results of a query applied to its corresponding bubble page. The number of pages M equals the minor loop length and N, the page size, equals the number of minor loops in the bubble memory. A systematic series of performance-improving access strategies and architectural modifications are applied to an existing major/minor loop bubble device to determine the effects of each change. In all cases data access-time formulas reveal that positioning a marked page for access is a linear function of the minor loop length M, while outputting the marked pages via the bubbles serial output bus is a quadratic function of M. An evaluation and relative comparison of these architectures indicate that a segmented, nondestructive major/minor loop transfer function can enhance current magnetic bubble memory (MBM) performance in relational data processing by an order of magnitude. View full abstract»

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  • A Hierarchical Routing and Flow Control Policy (HRFC) for Packet Switched Networks

    Publication Year: 1980 , Page(s): 971 - 977
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2572 KB)  

    A new policy that can effectively handle message routing and flow control simultaneously in a packet switched computer network is presented. In such a policy, a traffic threshold level is assigned for each channel in the network. If all the channels along the preassigned primary route from current node to its destination do not exceed the predetermined traffic threshold, then the primary route is used. Otherwise, alternative route(s) are used to share the traffic load. When all the alternative routes from a source to a destination become unavailable, then the input traffic from that source to that destination is temporarily rejected. Simulation results of the behavior and performance of such a routing and flow control policy are presented. The implementation of the policy is also discussed. Simulation results reveal that this new policy is simpler to implement and yields better performance than that of distributed routing algorithm and buffer allocation flow control policy, which are currently being used in many packet switched networks. View full abstract»

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  • Identification of Equivalent Faults in Logic Networks

    Publication Year: 1980 , Page(s): 978 - 985
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1652 KB)  

    The properties of combinational logic functions and networks that influence equivalence among stuck-type faults are investigated. It is shown that the equivalence of certain types of faults depends only on the function being realized. For instance, the fault classes among primary input/output faults are of this type. It is shown that every irredundant realization of the two-variable EXCLUSIVE-OR function has a unique set of ten fault classes. A fault class F in a module M contained in a network N is called intrinsic, if F can be determined from M alone, i. e., F is independent of N. Using the concepts of intrinsic equivalence and inversion parity, conditions for the equivalence and nonequivalence of two fault classes are obtained. These results are applied to the problem of equivalence identification in two-level logic networks where they provide a substantial reduction in the amount of computation required. View full abstract»

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  • On the Properties and Applications of Fuzzy-Valued Switching Functions

    Publication Year: 1980 , Page(s): 986 - 994
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2803 KB)  

    A fuzzy-valued switching function F over n variables is a mapping from Vn to V where V represents the closed unit interval [0,1] such that F is representable by a logic formula defined under the operations of fuzzy algebra. View full abstract»

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  • A Queueing Theory-Based Analytic Model of a Distributed Computer Network

    Publication Year: 1980 , Page(s): 994 - 1001
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3636 KB)  

    This paper describes the development of an analytic model for performance studies of distributed computer networks. The model factors each node of a network into processing and channel components and models each separately using M/D/r and M/M/l queues. The model also includes a correction factor to account for the nonexponential nature of the input to the channel component. Results produced by the model are compared with results previously reported in the literature to estimate the magnitude of improvement which can be expected. View full abstract»

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  • A Unified Reliability Model for Fault-Tolerant Computers

    Publication Year: 1980 , Page(s): 1002 - 1011
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2886 KB)  

    The diversified nature of fault-tolerant computers led to the development of a multiplicity of reliability models which are seemingly unrelated to each other. As a result, it becomes difficult to develop automated tools for reliability analysis which are both general and efficient. Thus, the potential of reliability modeling as a practical and useful tool in the design process of fault-tolerant computers has not been fully realized. This paper summarizes the results of an extended effort to develop a unified approach to reliability modeling of fault-tolerant computers which strikes a good compromise between generality and practicality. The unified model developed encompasses repairable and nonrepairable systems and models, transient as well as permanent faults, and their recovery. Based on the unified model, a powerful and efficient reliability estimation program ARIES has been developed. View full abstract»

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  • Correction to "Syndrome-Testable Design of Combinational Circuits"

    Publication Year: 1980 , Page(s): 1012 - 1013
    Cited by:  Papers (7)
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  • Synthesis of Combinational Logic Using Decomposition and Probability

    Publication Year: 1980 , Page(s): 1013 - 1016
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (751 KB)  

    A new algorithm for the synthesis of single-output two-valued combinational logic using decomposition and probability is described. Two probabilistic quantities, the probability of existence of all pertinent decomposition classes, and the probable cost of an N variable function are defined. Results for completely specified functions are derived and tabulated. The extension to incompletely specified functions is discussed. A randomly chosen function is assumed throughout the paper. View full abstract»

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  • An Efficient Method for Improving Reliability of a Pipeline FFT

    Publication Year: 1980 , Page(s): 1017 - 1020
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (710 KB)  

    A technique is described whereby the reliability of a pipeline FFT structure can be significantly increased with a relatively modest increase in complexity/cost. The proposed method is shown to give a substantial reliability/cost improvement relative to that achievable with dual redundant structures. View full abstract»

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  • Synchronous Sequential Machines: A Modular and Testable Design

    Publication Year: 1980 , Page(s): 1020 - 1025
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1028 KB)  

    It will be shown that a single-input n-definite machine realized by a universal modular tree, in which each module consists of AND-EXCLUSIVE-OR-DELAY (AND-EOR-DELAY) as a basic element, can be tested for single stuck-type-faults by tests of length 2n + 3 only. This is a marked improvement over the previous results for trees consisting of AND-OR-DELAYS, which are known to have test lengths of exponential growth. View full abstract»

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  • Dual-Mode Logic for Function-Independent Fault Testing

    Publication Year: 1980 , Page(s): 1025 - 1029
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1003 KB)  

    This correspondence presents a oncept of function-independent testing of digital networks. It is based on the idea of dual-mode logic where the network is tested in one mode while the normal function of the network is performed in another mode, with neither mode interfering with the other. This correspondence simultaneously defines the structure of modules with the above characteristics such that combinational and sequential networks built with them can be tested with two and six function-independent tests, respectively. View full abstract»

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  • Construction of a Generalized Connector with 5.8 n log2n Edges

    Publication Year: 1980 , Page(s): 1029 - 1032
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (885 KB)  

    In this correspondence we present a simple construction of a generalized connector with 5.8n log2n edges, which is an improvement over a previous construction proposed by Thompson and requiring 7.6n log2n edges. Specifically, we propose a construction for a generalizer with only 2n log2n edges as against that proposed by Thompson with 3.8n log2n edges. View full abstract»

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  • On Negabinary-Binary Arithmetic Relationships and Their Hardware Reciprocity

    Publication Year: 1980 , Page(s): 1032 - 1035
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (676 KB)  

    This correspondence emphasizes the close relationship between binary addition and negative negabinary addition (n.n.b.a.). This is established by describing two possible ways of utilizing binary adders for performing n.n.b.a. Similar techniques of using n.n.b.a. adders for binary addition are also outlined and thus, negative addition is seen to be a primitive operation. These algorithms lead to four simple conversion processes of numbers from binary to negabinary system and vice versa. View full abstract»

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  • Machine Processing of Remotely Sensed Data

    Publication Year: 1980 , Page(s): 1035-a
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    Freely Available from IEEE
  • IEEE Computer Society Publications

    Publication Year: 1980 , Page(s): 1035
    Save to Project icon | Request Permissions | PDF file iconPDF (148 KB)  
    Freely Available from IEEE
  • Advance Announcement... Tutorial Week 80

    Publication Year: 1980 , Page(s): 1035
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    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org