IEEE Transactions on Computers

Issue 9 • Sept. 1979

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  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1979, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1979, Page(s): c2
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  • Introduction to Special Section on Programmable Logic Arrays

    Publication Year: 1979, Page(s): 593
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1413 KB)

    IN AN earlier paper [1], aspects of LSI were discussed that provide strong motivation for using programmed logic arrays for implementation of computer functions. These factors include extended use of a single chip design, the necessity to design for function, effective fault analysis and testing, and minimal design errors and changes. The approach to LSI exemplified by PLA's will continue to be us... View full abstract»

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  • A Programmable Logic Approach for VLSI

    Publication Year: 1979, Page(s):594 - 601
    Cited by:  Papers (26)  |  Patents (49)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2737 KB)

    This paper explores the use of a proposed programmable storage/logic array (SLA) chip as a general purpose universal logic element for digital computers. The SLA is compared to other programmable logic arrays in implementation and utilization, showing how it permits construction of complete digital subsystems on one chip without sacrifice in programmability. When compared with other contending ver... View full abstract»

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  • A High Density Programmable Logic Array Chip

    Publication Year: 1979, Page(s):602 - 608
    Cited by:  Papers (45)  |  Patents (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2219 KB)

    A programmable logic array (PLA) chip design using special array folding techniques and an on-chip bus structure has been developed. It overcomes the sparseness in conventional large PLA configurations. The design is a masterslice FET chip personalized for the particular application during processing. Software algorithms are used to map conventional PLA formats into the new structure. The techniqu... View full abstract»

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  • Logic Design of Programmable Logic Arrays

    Publication Year: 1979, Page(s):609 - 617
    Cited by:  Papers (27)  |  Patents (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2440 KB)

    Compared with random logic circuits, memory-type circuits are more suitable for LSI realization since their iterated structure of identical cells results in higher transistor density and higher yield. A programmable logic array (PLA) is a read only memory (ROM) with programmable addresses and it is suitable for realizing logic functions with many unspecified input combinations. For such a function... View full abstract»

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  • Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's)

    Publication Year: 1979, Page(s):617 - 627
    Cited by:  Papers (77)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3970 KB)

    Programmable logic arrays (PLA's) are the logic implementation vehicle for many applications. Due to their regular structure, one is able to model and analyze many more of the likely physical faults than the conventional stuck faults considered for random combinational logic implementations. We investigate shorts between the lines and crosspoint defects (spurious absence or presence), as well as s... View full abstract»

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  • Associative-Search Bubble Devices for Content-Addressable Memory and Array Logic

    Publication Year: 1979, Page(s):627 - 636
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2401 KB)

    Bubble latches (switches with memory capability) provide very simple associative-search devices in shift-register type memories. Such devices allow a simple implementation of content-addressable memories (CAM's), only requiring small addition of area, circuits, and interconnections to those of a conventional shift-register memory. Moreover, such devices, in combination with a multi-input or circui... View full abstract»

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  • Pseudo-Random Number Generator Based on Binary and Quinary Maximal-Length Sequences

    Publication Year: 1979, Page(s):637 - 642
    Cited by:  Papers (2)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1976 KB)

    A new pseudo-random generator for decimal numbers is presented. A sequence of decimal digits is obtained by combining a binary and a quinary maximal-length sequence generated by feedback shift-register circuits. The autocorrelation sequence (ACS) of the resulting decimal sequence is calculated; it shows that linear dependencies are extremely small. Finally, guidelines are developed for choosing fe... View full abstract»

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  • Algorithms for Reporting and Counting Geometric Intersections

    Publication Year: 1979, Page(s):643 - 647
    Cited by:  Papers (372)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2206 KB)

    An interesting class of "geometric intersection problems" calls for dealing with the pairwise intersections among a set of N objects in the plane, These problems arise in many applications such as printed circuit design, architectural data bases, and computer graphics. Shamos and Hoey have described a number of algorithms for detecting whether any two objects in a planar set intersect. In this pap... View full abstract»

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  • Minimum Parallel Binary Adders with NOR (NAND) Gates

    Publication Year: 1979, Page(s):648 - 659
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3328 KB)

    Parallel binary adders of n bits long in single-rail input logic which have a minimum number of NOR gates are derived in this paper. The minimality of the number of NOR gates is proved for an arbitrary value of n. Also, it is proved that the adders must be a cascade of basic modules and that there exist many different types of basic modules. These adders have fewer gates and shorter net gate delay... View full abstract»

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  • Time and Parallel Processor Bounds for Fortran-Like Loops

    Publication Year: 1979, Page(s):660 - 670
    Cited by:  Papers (58)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3100 KB)

    The main goal of this paper is to show that a large number of processors can be used effectively to speed up simple Fortran-like loops consisting of assignment statements. A practical method is given by which one can check whether or not a statement is dependent upon another. The dependence structure of the whole loop may be of different types. For each type, a set of time and processor upper boun... View full abstract»

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  • On Minimum Cost Recovery from System Deadlock

    Publication Year: 1979, Page(s):671 - 677
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2309 KB)

    In this paper we consider the problem of finding a minimum cost deadlock recovery. We show that the problem is NP-complete and hence an efficient algorithm is unlikely to exist for this problem. We propose three fast heuristics and analyze their worst case performance relative to optimal solutions. Finally, we perform some simulation tests to get a feel for the average performance of these heurist... View full abstract»

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  • Interleaved Memory Bandwidth in a Model of a Multiprocessor Computer System

    Publication Year: 1979, Page(s):678 - 681
    Cited by:  Papers (32)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1819 KB)

    An approximate analysis is performed of an often studied model of an interleaved memory, multiprocessor system consisting of M memory modules and N processors. A closed-form solution is obtained and the one approximation used is found to result in negligible error. This solution is about an order of magnitude more accurate than the best previous result. View full abstract»

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  • Conservative Logic Elements and Their Universality

    Publication Year: 1979, Page(s):682 - 685
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (654 KB)

    A conservative logic element (CLE) is a multiple-output logic element whose weight of an input vector is equal to that of the corresponding output vector, and fan-out of each output terminal is restricted to one. A CLE is a generalized model of magnetic bubble logic elements, etc. In order to realize an arbitrary function, it is necessary to use constant-supplying elements (CSE's). In this corresp... View full abstract»

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  • Properties of Transparent Shortened Codes for Memories With Stuck-at Faults

    Publication Year: 1979, Page(s):686 - 690
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (953 KB)

    This correspondence deals with the problem of selecting optimal shortened d = 3 Hamming codes and d = 4 extended Hamming codes. The studied codes are transparent codes, minimum column weight codes, and codes with a minimum number of codewords of minimum weight. It is concluded that a shortened code normally does not combine the properties of being transparent, being of minimum column weight type a... View full abstract»

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  • How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs

    Publication Year: 1979, Page(s):690 - 691
    Cited by:  Papers (627)  |  Patents (48)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (465 KB)

    Many large sequential computers execute operations in a different order than is specified by the program. A correct execution is achieved if the results produced are the same as would be produced by executing the program steps in order. For a multiprocessor computer, such a correct execution by each processor does not guarantee the correct execution of the entire program. Additional conditions are... View full abstract»

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  • Comments on "An Approach to Highly Integrated Computer-Maintained Cellular Arrays"

    Publication Year: 1979, Page(s):691 - 693
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (699 KB)

    The above paper1describes machines constructed on faulty logic arrays. These machines use some or all of the good cells that form a connective cluster. It is pointed out here that when the faulty cells are randomly distributed over the array, the propagation of a freely expanding signal, which must avoid the faulty cells, is a percolation process. The percolation process determines the ... View full abstract»

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  • Comment on "The Focus Number System"

    Publication Year: 1979, Page(s): 693
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (254 KB)

    In a recent correspondence1Lee and Edgar present a logarithmic number system and describe algorithms for the four basic arithmetic operations. Although it is encouraging to see continued interest in the area of specialized number systems, Lee and Edgar's work represents a duplication of work published in this TRANSACTIONS in 1975[1]. View full abstract»

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  • Addendum to "The Focus Number System"

    Publication Year: 1979, Page(s): 693
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (254 KB)

    In 1971 Kinsbury and Rayner, publishing under the title "Digital Filtering Using Logarithmic Arithmetic" [1] disclosed a sign-plus-logarithm number system, and a means of performing addition through single dimensional lookup using the formula c = b + F(a − b). The system was demonstrated on a computer. In 1975 Swartzlander and Alexopoulos disclosed Kinsbury's logarithmic arithmetic as "The S... View full abstract»

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  • if your computer engineering library doesn't subscribe to all 4 it's not complete.

    Publication Year: 1979, Page(s): 693
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  • Announcing a new Quarterly IEEE Transactions ... IEEE Transactions on Pattern Analysis and Machine Intelligence

    Publication Year: 1979, Page(s): 693
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  • Call for Papers

    Publication Year: 1979, Page(s): 693
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    Freely Available from IEEE
  • IEEE Computer Society Publications

    Publication Year: 1979, Page(s): 693
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    Freely Available from IEEE
  • Announcing... The IEEE Computer Society's Tutorial Week 79

    Publication Year: 1979, Page(s): 693
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org