IEEE Transactions on Computers

Issue 3 • March 1979

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  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1979, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1979, Page(s): c2
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  • Editor's Notice

    Publication Year: 1979, Page(s): 177
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  • On a Ternary Model of Gate Networks

    Publication Year: 1979, Page(s):178 - 184
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2496 KB)

    In this paper we formalize a ternary model which is being used to study the behavior of binary sequential gate networks. We first describe a binary model which is capable of a detailed description of network behavior, but involves a number of steps that grows exponentially in the number of gates. The complexity of the ternary model is linear in the number of gates;however, only partial information... View full abstract»

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  • Associative Processing of Network Flow Problems

    Publication Year: 1979, Page(s):184 - 190
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3673 KB)

    Application of associative processors to the solution of the maximal flow problem is investigated. To take maximum advantage of the capability of associative processors, a new algorithm based on matrix representation is developed. The new algorithm is then compared with the associative version of the Ford and Fulkerson labeling method. The comparison is made on the total associative memory access ... View full abstract»

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  • Program Behavior and the Performance of Interleaved Memories

    Publication Year: 1979, Page(s):191 - 199
    Cited by:  Papers (12)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2952 KB)

    One of the major factors influencing the performance of an interleaved memory system is the behavior of the request sequence, but this is normally ignored. This paper examines this issue. Using trace driven simulations it is shown that the commonly used assumption, that each request is independently and equally likely to be to any module, is not valid. The duality of memory interference with pagin... View full abstract»

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  • Implementing Parallel Counters with Four-Valued Threshold Logic

    Publication Year: 1979, Page(s):200 - 204
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1931 KB)

    Parallel counters are multiple-input circuits that count the number of their inputs that are in a given state. They are useful in implementing parallel multipliers, digital summers, digital correlators, and in other digital signal processing capacities. In this paper, the implementation of parallel counters with four-valued threshold logic is described and these implementations are compared to the... View full abstract»

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  • The Solution of Differential Equations on Short-Word-Length Computing Devices

    Publication Year: 1979, Page(s):205 - 214
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2821 KB)

    When the numerical solution of differential equations (DE's) for dynamical simulation is performed with short-word-length computing devices, it is essential that truncation (round-off) error be understood and controlled where possible. This paper presents a simple but enlightening analysis of truncation errors in the computer solution of DE's, an analysis which develops the rationale for the resid... View full abstract»

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  • High-Speed Arithmetic Arrays

    Publication Year: 1979, Page(s):215 - 224
    Cited by:  Papers (24)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2781 KB)

    High-speed multifunction arithmetic arrays for multiplication, division, square and square-root operations are presented in this paper. These arrays seem attractive due to their versatility and speed. A recently described quotient-bit evaluation technique that uses the carry-save method in a nonuniform division array is extended here for the restoring-division process. This array includes the mult... View full abstract»

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  • Processes for Random and Sequential Accessing in Dynamic Memories

    Publication Year: 1979, Page(s):225 - 237
    Cited by:  Papers (3)  |  Patents (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2764 KB)

    In a memory using shuffle interconnections, the concept of sequential accessing in unit time has been related to the existence of a sequence of operations, called a tour, that moves each datum through the read/write port. For memories of size 32, it has been stated that for certain operations no tours exist at window 1; moreover, the existence and construction of tours at other windows and for lar... View full abstract»

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  • An Algorithm to Dualize a Regular Switching Function

    Publication Year: 1979, Page(s):238 - 243
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (960 KB)

    Given a monotone (nondecreasing) switching function F(x1,···,xn), its prime implicants are the minimal infeasible points, i.e., the minimal solutions to F(x) = 1. A monotone F is regular ifany "right shift" of a feasible point is again feasible. The roofs of a regular function F are those prime implicants al ofwhose right shifts are feasible. The set of these r... View full abstract»

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  • An Efficient Algorithm for Determining Hadamard Sequency Vectors

    Publication Year: 1979, Page(s):243 - 244
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (377 KB)

    An efficient algorithm for determining the sequency vector S̄nof a 2n× 2nHadamard matrix is developed. The method requires fewer computation steps than a previously known method. View full abstract»

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  • Analysis of the Signal Reliability Measure and an Evaluation Procedure

    Publication Year: 1979, Page(s):244 - 249
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1072 KB)

    The classical reliability measure of digital circuits, known as functional reliability, assumes that the circuit fails whenever a fault is present in it. It has long been known that this reliability measure is overly pessimistic since digital circuits may produce correct output signals even when some faults are present in them. A different reliability measure, known as signal reliability, is the p... View full abstract»

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  • Aspects of the Upper Bounds of Finite Input-Memory and Finite Output-Memory Sequential Machines

    Publication Year: 1979, Page(s):249 - 253
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (892 KB)

    In this paper upper bounds on the finite input-memory μiand finite output-memory μoof n-state completely specified sequential machines (CSSM's) and incompletely specified sequential machines (ISSM's) are investigated. It is observed through computational means that N = n(n − 1)/2 is not a tight upper bound for finite input-memory of ISSM's and finite output-me... View full abstract»

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  • Comments on "A Readily Implemented Single-Error-Correcting Unit-Distance Counting Code"

    Publication Year: 1979, Page(s):253 - 255
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (565 KB)

    Kautz, in the above paper1has presented a method of correcting single errors in SIB3codes that does not displace the count by more than two counts in the counting sequence, assuming the two most significant bits are correct. This paper presents a correction method that does not require the two most significant bits to be correct and does not displace the count by more than on... View full abstract»

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  • Comments on "A New Random-Error-Correction Code"

    Publication Year: 1979, Page(s):255 - 257
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (662 KB)

    This correspondence investigates the error propagation properties of six different systems using a (12, 6) systematic double-error-correcting convolutional encoder and a one-step majority-logic feedback decoder. For the generally accepted assumption that channel errors are much more likely to occur than hardware errors in the decoder, it is shown that the system proposed by Massey outperforms the ... View full abstract»

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  • Author's Reply2

    Publication Year: 1979, Page(s):257 - 258
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (443 KB)

    Without proof Paaske3states that "... En1cannot be true." Paaske's statement is based on his qualitative assumption that channel error is "much more likely" to occur than a hardware error in the decoder. The author will show that En's statements are still true under Paaske's assumption. Previous correspondence was cited by Paaske and claimed to be "the best way..." to judge a... View full abstract»

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  • Comments on "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories"

    Publication Year: 1979, Page(s):258 - 261
    Cited by:  Papers (61)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (542 KB)

    An efficient, optimal test sequence for detecting multiple stuck-at faults in random access memories (RAM's) for any decoder implementation is presented. Another algorithm which does not assume any particular wired logic behavior of simultaneously accessed storage locations, is also presented. View full abstract»

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  • Comments on "Redundancy Testing in Combinational Networks"

    Publication Year: 1979, Page(s):261 - 262
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (326 KB)

    In the above-mentioned paper1, Lee and Davidson present an algorithm for detecting all single redundant lines in a tree-type NAND network. In order to test for a single redundancy in a nontree network, they suggest replicating portions of the network (those which fan out) to get an equivalent tree-type NAND network. The algorithm for detecting single redundancies can then be applied to ... View full abstract»

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  • Experiments with a Density Router for PC Cards

    Publication Year: 1979, Page(s):262 - 267
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (947 KB)

    In this correspondence a new routing cost function is defined which is a function of local blockage density in addition to path length. A parameter α specifies the degree to which density is to influence the cost. The use of such a cost function results in what we refer to as a density router. The classical Lee router is a special case of the density router with α equal to 0. We present ... View full abstract»

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  • On the Equivalence Between One-Dimensional Discrete Walsh-Hadamard and Multidimensional Discrete Fourier Transforms

    Publication Year: 1979, Page(s):267 - 268
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (339 KB)

    It is shown that the discrete Walsh–Hadamard transform applied to 2none-dimensional data is equivalent to the discrete n-dimensional Fourier transform applied to the same 2ndata arranged on the binary n-cube. A similar relationship is valid for the generalized discrete Walsh transform suggested by Andrews and Caspari. This relationship explains the theorem concerning th... View full abstract»

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  • On the Properties of Sensitized Paths

    Publication Year: 1979, Page(s):268 - 269
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    In this note we investigate the conditions under which the paths which propagate a fault in a combinational network to the network output are not necessarily entirely sensitized. View full abstract»

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  • Revision of the Buffer Length Derivation for a Modified Ek/D/1 Systems by Maritsas and Hartley

    Publication Year: 1979, Page(s):269 - 273
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1878 KB)

    The problem of loss of items arriving at a queue of limited length is relevant to the design of computers with real-time inputs and of similar equipments where only a limited input buffer size is possible. The length of buffer required to reduce the overflow loss to an acceptably low level is an important design parameter. View full abstract»

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  • The Anomalous Behavior of Flip-Flops in Synchronizer Circuits

    Publication Year: 1979, Page(s):273 - 276
    Cited by:  Papers (18)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1895 KB)

    Quantitative results of the observations of oscillatory and metastable behavior of common flip-flops in response to logically undefined input conditions, such as those that occur in synchronizers and arbiters, are presented. The results are obtained with the help of a circuit developed for this purpose which measures the failure rate for a certain flip-flop and frequency. It is found that the obta... View full abstract»

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  • Unified Design of Self-Checking and Fail-Safe Combinational Circuits and Sequential Machines

    Publication Year: 1979, Page(s):276 - 281
    Cited by:  Papers (49)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1027 KB)

    This correspondence deals with a unification and extension of some previous work on self-checking (SC) and fail-safe (FS) systems. View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org