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IEEE Transactions on Computers

Issue 10 • Oct. 1979

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Displaying Results 1 - 23 of 23
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1979, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1979, Page(s): c2
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  • Binary Routing Networks

    Publication Year: 1979, Page(s):699 - 703
    Cited by:  Papers (10)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2142 KB)

    The design of a communications network based on simple routing of packets through the network and suitable for use in local systems is presented. Several network topologies are considered using differing node structures. Generation of routing information is discussed together with flow control. It is shown that high performance is easily obtained and the system drawbacks do not affect the design f... View full abstract»

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  • A Multicomputer System with Dynamic Architecture

    Publication Year: 1979, Page(s):704 - 721
    Cited by:  Papers (26)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6316 KB)

    This paper considers the organization of certain multicomputer systems with a particular type of dynamic architecture. The system allows one to reconfigure via software available hardware resources (widths of processors, memories, and I/O units), forming computers with different word sizes. A multicomputer system is formed from identical dynamic computer groups. Each group may assume a variety of ... View full abstract»

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  • An 0(n) Parallel Multiplier with Bit-Sequential Input and Output

    Publication Year: 1979, Page(s):721 - 727
    Cited by:  Papers (40)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3128 KB)

    Previous proposals for fast multipliers are discussed, along with a summary of the known theoretical limitations of such designs. Then, a new parallel multiplier with a very simple configuration is suggested. This multiplier operates in time 0(n), where n is the maximum of the lengths of the multiplier and multiplicand, both of which are fixed point, expressed in binary notation. It is a logical c... View full abstract»

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  • A High-Speed Algorithm for the Generation of Straight Lines and Circular Arcs

    Publication Year: 1979, Page(s):728 - 736
    Cited by:  Papers (22)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2398 KB)

    Incremental generation of straight lines and circular arcs is important in various fields such as graphic displays, digital plotters, and numerical control systems. An improved algorithm of incremental curve generation called a modified displacement comparison method (MDCM) is proposed. View full abstract»

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  • Analysis of Update Synchronization for Multiple Copy Data Bases

    Publication Year: 1979, Page(s):737 - 747
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3374 KB)

    A formal model allowing a precise definition of coherence and promptness in a multiple copy information system is presented and used to analyze a class of update synchronization techniques. View full abstract»

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  • Structured Design of Substitution-Permutation Encryption Networks

    Publication Year: 1979, Page(s):747 - 753
    Cited by:  Papers (46)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3316 KB)

    In attempting to solve the problems of data security, researchers, and practititioners are placing increasing emphasis on encryption. An important class of encryption schemes is that of substitution-permutation (SP) encryption networks. A variant of the SP network has been chosen by the National Bureau of Standards as the data encryption standard. In this paper, we introduce the concept of complet... View full abstract»

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  • An Abstract Model for Digital System Fault Diagnosis

    Publication Year: 1979, Page(s):754 - 767
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2531 KB)

    An abstract model applicable to the use of both diagnostic programs and hardware diagnostic aids in digital systems is presented. The model is capable of dealing with replaceable units having a variety of complexity and is shown in a mathematically rigorous fashion to encompass existing models for diagnosis. A three-level structure for representing faults and a two-level structure for representing... View full abstract»

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  • Synthesis of Gate-Minimum Multi-Output Two-Level Negative Gate Networks

    Publication Year: 1979, Page(s):768 - 772
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1818 KB)

    A negative gate is a gate which can realize an arbitrary negative function. The problem of synthesizing logical networks, with negative gates only, is important for the design of MOS LSI. View full abstract»

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  • The Complexity of Monotone Networks for Certain Bilinear Forms, Routing Problems, Sorting, and Merging

    Publication Year: 1979, Page(s):773 - 782
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3006 KB)

    In this paper, we consider the size of combinational switching networks required to synthesize monotone Boolean functions using only operations from the functionally incomplete set of primitives {disjunction, conjunction}. A general methodology is developed which is used to derive Q(n log n) lower bounds on the size of monotone switching circuits for certain bilinear forms (including Toeplitz and ... View full abstract»

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  • A Note on Open Shop Preemptive Schedules

    Publication Year: 1979, Page(s):782 - 786
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3180 KB)

    The problem of preemptively scheduling a set of n independent jobs on an m processor open shop is discussed. An algorithm to construct preemptive schedules with minimum-maximum finishing time is presented. The worst case time complexity is 0(r + min {m4, n4, r2}), where r is the number of nonzero tasks. The maximum number of preemptions introduced is 0(min {rn, rm,... View full abstract»

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  • On Analytical Modeling of Intermittent Faults in Digital Systems

    Publication Year: 1979, Page(s):786 - 791
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2301 KB)

    This correspondence discusses three analytical models for intermittent faults in digital systems. These models attempt to represent the stochastic behavior of intermittent faults accurately. The models find applicatiońs in predicting the performance of fault detection algorithms. A fault detection procedure is described and its performance is examined based on the analytical models. A numeric... View full abstract»

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  • Ordering of Connections for Automated Routing

    Publication Year: 1979, Page(s):791 - 794
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (586 KB)

    Ordering of connections is one of the key areas in automated layout design of printed circuit boards. A simple heuristic algorithm to decide the priority of connections is discussed in this paper. It makes use of six interference matrices to calculate a measure of the interference a connection causes to all other connections on the board and this forms the basis of the ordering. View full abstract»

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  • Fully Interconnecting Multiple Computers with Pipelined Sorting Nets

    Publication Year: 1979, Page(s):795 - 798
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (841 KB)

    A pipelined multiprocessor interconnection method functionally equivalent to a full crossbar, but with a per processor cost proportional to the square of the log of the total number of processors, is presented. View full abstract»

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  • A New Approach to 2-Asummability Testing

    Publication Year: 1979, Page(s):798 - 801
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (892 KB)

    A relationship between 2-monotonicity and 2-asummability has been established and thereby a fast method for testing 2-asummability of switching functions derived. The approach is based on the fact that only a particular type of 2-sums need be examined for 2-asummability testing of 2-monotonic switching functions. These 2-sums are those which contain more than five 1's. 2-asummability testing for t... View full abstract»

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  • On Necessary and Sufficient Conditions for Multiple Fault Undetectability

    Publication Year: 1979, Page(s):801 - 802
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (418 KB)

    This correspondence states necessary and sufficient conditions for a multiple stuck-at fault in a combinational network to be undetected by a test set. The conditions are given in terms of fault masking relationships. It is shown that several other statements on this subject which have appeared in the literature are invalid. View full abstract»

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  • Comments on "A Note on Synchronizer or Interlock Maloperation"

    Publication Year: 1979, Page(s):802 - 804
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2778 KB)

    E. G. Wormald's note1proposes a way to prevent metastable action in synchronizers. Experimental results from testing his suggested circuits show that his solution does not work. A reference to a general proof that synchronizers must have a region of metastable action is given. View full abstract»

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  • Support for T. J. Chaney's Comments on "A Note on Synchronizer or Interlock Maloperation"

    Publication Year: 1979, Page(s): 804
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1309 KB)

    Chaney's masterful exposition [1] on my suggestion [2] for defeating synchronizer or interlock maloperation should provide some much needed publicity for the nature and possible effects of synchronizer metastability. Hopefully, the discussion will discourage further attempts to eliminate this unavoidable characteristic. View full abstract»

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  • Comments on "Multiple Fault Detection in Combinational Network"

    Publication Year: 1979, Page(s):804 - 805
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1354 KB)

    In the above paper,1the authors have defined complete test, closed fault set, fault set graph, and undetected fault set as follows. View full abstract»

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  • 5th International Conference on Pattern Recognition

    Publication Year: 1979, Page(s): 805
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    Freely Available from IEEE
  • IEEE Computer Society Publications

    Publication Year: 1979, Page(s): 805
    Request permission for commercial reuse | PDF file iconPDF (152 KB)
    Freely Available from IEEE
  • Announcing... The IEEE Computer Society's Tutorial Week 79

    Publication Year: 1979, Page(s): 805
    Request permission for commercial reuse | PDF file iconPDF (2019 KB)
    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org