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IEEE Transactions on Computers

Issue 12 • Date Dec. 1978

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Displaying Results 1 - 25 of 32
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1978, Page(s): c1
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    Freely Available from IEEE
  • IEEE Computer Society

    Publication Year: 1978, Page(s): c2
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    Freely Available from IEEE
  • Fault Detection Capabilities of Alternating Logic

    Publication Year: 1978, Page(s):1093 - 1098
    Cited by:  Papers (75)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2280 KB)

    This paper details the fault detection capability of a design technique named "alternating logic design." The technique achieves its fault detection capability by utilizing a redundancy in time instead of the conventional redundancy in space and is based on the successive execution of a required function and its dual. In combinational networks the method involves the utilization of a self-dual fum... View full abstract»

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  • An Algorithm for Optimal NAND Cascade Logic Synthesis

    Publication Year: 1978, Page(s):1099 - 1111
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3226 KB)

    This paper is concerned with optimal synthesis of switching logic by a limited depth tree-like network, the NAND cascade. This cascade consists of a number of complete three-level, fan-in restricted NAND trees feeding a NAND collector. The goal of the proposed synthesis is to minimize the number of NAND trees of the cascade, which in turn will minimize its overall depth, i.e., the delay time of th... View full abstract»

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  • A New Solution to Coherence Problems in Multicache Systems

    Publication Year: 1978, Page(s):1112 - 1118
    Cited by:  Papers (243)  |  Patents (67)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2325 KB)

    A memory hierarchy has coherence problems as soon as one of its levels is split in several independent units which are not equally accessible from faster levels or processors. The classical solution to these problems, as found for instance in multiprocessor, multicache systems, is to restore a degree of interdependence between such units through a set of high speed interconnecting buses. This solu... View full abstract»

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  • Generalized Connection Networks for Parallel Processor Intercommunication

    Publication Year: 1978, Page(s):1119 - 1125
    Cited by:  Papers (64)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2727 KB)

    A generalized connection network (GCN) is a switching network with N inputs and N outputs that can be set to pass any of the NNmappings of inputs onto outputs. This paper demonstrates an intimate connection between the problems of GCN construction, message routing on SIMD computers, and "resource partitioning." A GCN due to Ofman [7] is here improved to use less than 7.6N log N contact ... View full abstract»

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  • A Stochastic Model for Closed-Loop Preemptive Microprocessor I/O Organizations

    Publication Year: 1978, Page(s):1126 - 1136
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2453 KB)

    A stochastic model of closed-loop priority I/O systems is developed in which request generation is assumed to be exponential but service time distributions are arbitrary. This model reflects the code granularity caused by the implementation. Using this model, an interrupt-driven system is compared to a similar system with polled I/O on the basis of latency times and CPU utilization. View full abstract»

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  • A New Double-Rank Realization of Sequential Machines

    Publication Year: 1978, Page(s):1137 - 1143
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2047 KB)

    A new type of double-rank sequential circuit is presented in this paper. This new type, called Type 4, differs from its predecessor types in that it employs a Boolean memory as rank-1 memory instead of flip-flops. The Boolean memory used is an aggregate of symmetric Boolean memories with 1-out-of-n state encodings. A procedure for realizing a sequential machine by a Type 4 double-rank sequential c... View full abstract»

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  • Polylinear Decomposition of Synchronous Sequential Machines

    Publication Year: 1978, Page(s):1144 - 1152
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2669 KB)

    The paper presents systematic procedures for decomposing a sequential machine into submachines some or all of which are realized by polylinear sequential circuits. This polylinear decomposition is based upon classes of subsets of the set of states which possess the substitution property rather than upon partitions with substitution property. These classes are easily found using the backward state ... View full abstract»

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  • On Modular Networks Satisfying the Shift-Register Rule

    Publication Year: 1978, Page(s):1153 - 1176
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4998 KB)

    This paper considers the synthesis of the network N which realizes the original program (problem oriented network) N is assembled from n unit modules partitioned into r categories (r ≥ 1) each of which is formed from identical modules. View full abstract»

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  • Method of Folding a Piecewise Polynomial Function in the Delta Function Integral Representation

    Publication Year: 1978, Page(s):1177 - 1178
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (326 KB)

    A simple procedure is presented for determining the folded form of a piecewise polynomial function in the delta function integral representation. The procedure is useful in evaluating the autocorrelation function by means of the algebraic convolution technique developed by Polge and Hays. View full abstract»

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  • An Efficient Coordinate Rotation Algorithm

    Publication Year: 1978, Page(s):1178 - 1180
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (469 KB)

    The rotation of a graphic display through an angle δ requires a large number of multiplies by sin δ and cos δ. The time required for these multiplies can be reduced an order of magnitude or more by the appropriate choice of δ. The values chosen depend upon the base r and the digits of accuracy d. View full abstract»

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  • Asymptotic Approximations for the Number of Fanout-Free Functions

    Publication Year: 1978, Page(s):1180 - 1183
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (609 KB)

    Expressions are derived for the approximate number of functions realized by various n-variable fanout-free networks. Six recently studied networks are considered. It is shown that the relative number of functions realized by two networks for small and large n is quite different in certain cases. View full abstract»

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  • On the Generation of Permutations in Magnetic Bubble Memories

    Publication Year: 1978, Page(s):1183 - 1185
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (517 KB)

    A better algorithm is presented for the generation of an arbitrary permutation in a model of magnetic bubble memories that have been investigated previously. View full abstract»

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  • Arithmetic Codes in Residue Number Systems with Magnitude Index

    Publication Year: 1978, Page(s):1185 - 1188
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (929 KB)

    The idea of adding a magnitude index to the residue representation of numbers is reconsidered. The range of a given residue number system is supposed to be divided into intervals of equal width, and the magnitude index of a number X is defined as an integer locating X into one of such intervals. It is shown that the redundancy implied by the use of the magnitude index allows error detection or cor... View full abstract»

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  • On the Minimization of the Control Store in Microprogrammed Computers

    Publication Year: 1978, Page(s):1189 - 1192
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (727 KB)

    A new approach is presented for the minimization of the word length of the control store in microprogrammed computers. Given the set of microinstructions and the set of microcommands of a microprogrammed computer a minimal subset of microcommands are determined so that every other microcommand not contained in this minimal subset to be generated from it by a single AND or OR gate. The problem of f... View full abstract»

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  • An algebraic construction for q-ary shift register sequences

    Publication Year: 1978, Page(s):1192 - 1195
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    Using the Euclidean Algorithm for polynomials over GF(q), an algebraic technique for the generation of q-ary shift register sequences of arbitrary length l, 1 ≤ l ≤ qm, is obtained, where q is a power of a prime number, q = pn, and m is the number of shift register stages. View full abstract»

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  • The Reliability of a Fault-Tolerant Configuration Having Variable Coverage

    Publication Year: 1978, Page(s):1195 - 1197
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (589 KB)

    An expression is derived for the reliability of an r-on-m fault-tolerant configuration (r spares supporting m identical operating units) when both the hazard and the coverage probability are functions of time. In addition, the coverage probability is allowed to be a function of the number of spares that have to be tested before an operational unit is found. View full abstract»

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  • On the Characteristics of a Simple Architecture for Finite Impulse Response Digital Filtering

    Publication Year: 1978, Page(s):1197 - 1202
    Cited by:  Papers (2)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1031 KB)

    This correspondence discusses some useful features of a simple architecture for the hardware realization of finite impulse response (FIR) digital filters. The architecture is especially suited to applications where significant bandwidth reduction and subsampling (decimation) are required. The architecture is shown to be capable of both real signal filtering and combined complex frequency translati... View full abstract»

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  • An Algorithm for Minimal TANT Network Generation

    Publication Year: 1978, Page(s):1202 - 1206
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (942 KB)

    An algorithm for constructing minimal TANT networks is presented. Using the upper prime permissible implicants as candidates, two particular networks, A and B, are constructed. Network A has the minimum number of third level gates among all networks that have the minimum number of second level gates. Network B has the minimum number of second level gates among all networks that have the minimum nu... View full abstract»

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  • Fault Detection in Bilateral Arrays of Combinational Cells

    Publication Year: 1978, Page(s):1206 - 1213
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1121 KB)

    Sufficient conditions are derived that make multidimensional bilateral arrays of combinational cells easily testable for single faults. These conditions are easily implemented during the initial design of the arrays. No restrictions are made on the interconnection patterns or directions of signal flow in the arrays. The conditions are equally applicable to synchronous and asynchronous arrays. No a... View full abstract»

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  • A Set of Invariants Within the Power Spectrum of Unitary Transformations

    Publication Year: 1978, Page(s):1213 - 1216
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB)

    This correspondence presents a device for designing unitary transformations based on the Hadamard transform process. The notion of "invariants" within the power spectrum of one-dimensional transformations is developed and the specific case of some widespread transformations is considered. The results are extended to two-dimensional transformations and a character recognition experiment using the i... View full abstract»

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  • Satellite Packet Switching with Global Assignments and Batch Poisson Arrivals

    Publication Year: 1978, Page(s):1216 - 1221
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (887 KB)

    A satellite packet switching multiaccess model which employs a global scheduling assignment scheme is described and analyzed for batch Poisson arrivals. System performance in terms of buffer overflow probability and system delay is analyzed and simulated. The numerical results, presented in graphical form, indicate that the performance improves as the population size M increases. For large value o... View full abstract»

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  • On the Existence of Combinational Logic Circuits Exhibiting Multiple Redundancy

    Publication Year: 1978, Page(s):1221 - 1225
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (937 KB)

    Multiple redundancy is a very complex form of redundancy about which little is known. This correspondence shows by construction that redundancy of any multiplicity can exist in an arbitrary combinational circuit, and that redundancy of any multiplicity ≥ 4 can exist in a tree circuit. Many examples are given. The correspondence concludes with a discussion of the effect multiple redundancy ca... View full abstract»

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  • Comments on "A Floating Point Multiplexed DDA System"

    Publication Year: 1978, Page(s): 1226
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    In a recent paper, Hannington and Whitehead1describe the design of a floating point digital differential analyzer (DDA). There are, however, shortcomings in the design which we will describe in this correspondence. View full abstract»

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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org