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IEEE Transactions on Computers

Issue 12 • Dec. 1977

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Displaying Results 1 - 25 of 29
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1977, Page(s): c1
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    Freely Available from IEEE
  • IEEE Computer Society

    Publication Year: 1977, Page(s): c2
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  • Multiple-Valued Logic: An Introduction and Overview

    Publication Year: 1977, Page(s):1181 - 1182
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1574 KB)

    MULTIPLE-VALUED logic has been a subject of research work for many years [1], [2]. Until the late 1960's most of the reported work was of a theoretical nature, leaving little impact on the firmly established binary approaches in the design of digital systems. Then, as LSI technology proceeded to develop rapidly, it became apparent that multiple-valued logic offers not only a rich logic structure, ... View full abstract»

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  • Application of Fuzzy Logic to Approximate Reasoning Using Linguistic Synthesis

    Publication Year: 1977, Page(s):1182 - 1191
    Cited by:  Papers (792)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4198 KB)

    This paper describes an application of fuzzy logic in designing controllers for industrial plants. A fuzzy logic is used to synthesize linguistic control protocol of a skilled operator. The method has been applied to pilot scale plants as well as in practical situations. The merits of this method and its usefulness to control engineering are discussed. An avenue for further work in this area is de... View full abstract»

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  • Three Cell Structures for Ternary Cellular Arrays

    Publication Year: 1977, Page(s):1191 - 1202
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3623 KB)

    Three particular cell structures are defined for use in ternary cellular arrays. Universal arrays for both general and symmetric functions are considered and the optimum size is found. Both optimal and nonoptimal universal arrays are given for these cases as well as arrays for the sum and carry functions for a ternary full adder. View full abstract»

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  • Logic Properties of Unate Discrete and Switching Functions

    Publication Year: 1977, Page(s):1202 - 1212
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4003 KB)

    The total and local unateness of discrete and of switching functions are studied from a theoretical point of view. One shows that the local unateness leads to the concept of hazard-free transition for a discrete function. Unate covers for discrete functions are defined: they are either the smallest unate functions larger than a discrete function, or the largest unate functions smaller than a discr... View full abstract»

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  • Static-Hazard-Free T-Gate for Ternary Memory Element and Its Application to Ternary Counters

    Publication Year: 1977, Page(s):1212 - 1221
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6829 KB)

    The ternary T-gate can be used as a basic building block to construct both combinational and sequential circuits. Since the T-gate is one kind of tree-type universal logic module, any combinational circuit can be built up with modular logic arrays. For constructing ternary memory elements, however, the T-gate is required to be static hazard-free. A theoretical study is done on the necessary condit... View full abstract»

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  • Implementation of Ternary Circuits with-Binary Integrated Circuits

    Publication Year: 1977, Page(s):1222 - 1233
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2216 KB)

    A general method for implementing ternary circuits with binary integrated circuits is described. The conditions are given for a particular technology to be able to implement ternary circuits. For TTL, COSMOS, and ECL technologies, the necessary circuits are developed. Formulas are provided to obtain the minimum circuit according to the particular function required. Simplification rules correspondi... View full abstract»

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  • Multivalued Integrated Injection Logic

    Publication Year: 1977, Page(s):1233 - 1241
    Cited by:  Papers (49)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3013 KB)

    A family of circuits for multivalued, in particular quaternary, integrated injection logic is described. The basic elements are the I2L current mirror and I2L threshold gates. View full abstract»

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  • Detection of Single, Stuck-Type Failures in Multivalued Combinational Networks

    Publication Year: 1977, Page(s):1242 - 1251
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2853 KB)

    This paper examines the problem of detecting single stuck-type faults in multivalued combinational circuits. The algebra employed is the generalized ternary algebra developed by Vranesic, Lee, and Smith. Many of the concepts already developed for fault detection in binary circuits generalized easily to the multivalued case. The special properties of multivalued circuits for this algebra simplifies... View full abstract»

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  • On Multivalued Multithreshold Networks Composed of Conventional Threshold Elements

    Publication Year: 1977, Page(s):1251 - 1257
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2880 KB)

    In this paper, we consider multivalued multithreshold networks (MVTN's) to realize multivalued logic functions. Transformations of multivalued functions into multivalued multithreshold functions, and network syntheses for MVTN's are described. There are three emphases on the MVTN's:1) any arbitrary multivalued function can be realized by an MVTN, 2) an MVTN can be composed of conventional threshol... View full abstract»

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  • An Inverted File Processor for Information Retrieval

    Publication Year: 1977, Page(s):1258 - 1267
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1865 KB)

    Response time in large, inverted file document retrieval systems is determined primarily by the time required to access files of document identifiers on disk and perform the processing associated with a Boolean search request. This paper describes a specialized computer system capable of performing these functions in hardware. Using this equipment, a complicated sample search involving 70 terms an... View full abstract»

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  • Stochastic Error-Correcting Syntax Analysis for Recognition of Noisy Patterns

    Publication Year: 1977, Page(s):1268 - 1276
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2567 KB)

    In this paper, a probabilistic model for error-correcting parsing with substitution, insertion, and deletion errors is introduced. The formulation of maximum-likelihood error-correcting parser (MLECP) by incorporating the noise model into stochastic grammars is also presented. The use of stochastic error-correcting parsers for recognition of noisy and/or distorted patterns results in a process of ... View full abstract»

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  • A New J-K Flip-Flop for Synchronizers

    Publication Year: 1977, Page(s):1277 - 1279
    Cited by:  Papers (7)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1599 KB)

    Anomalous gating of asynchronous signals in synchronizers and arbiter circuits may cause significant errors and system failures. Since the probability of logically undefined states at the output of flip-flops increases rapidly with clock rate, the errors were reduced by lower frequencies, at the price of severe time loss, until now. The paper presents a J-K flip-flop in which the duration of an os... View full abstract»

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  • A High-Speed Threshold Gate Multiplier

    Publication Year: 1977, Page(s):1279 - 1283
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (965 KB)

    A design for a multiplier is proposed which utilizes the extended switching properties of threshold elements. High-speed adders capable of adding more than two summands are constructed using minimal numbers of threshold gates. These are used to sum the partial products generated in the multiplication of two numbers. Several levels of these adders may be combined to reduce the number of summands to... View full abstract»

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  • Digital Hardware for Sine-Cosine Function

    Publication Year: 1977, Page(s):1283 - 1286
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2175 KB)

    The design of a high-speed digital processor for the sine and cosine functions is discussed. The hardware provides a significant speed advantage over software calculations of these functions. The special processor provides floating point results of 35 bit accuracy within 40 μs after the argument is loaded. This is faster by a factor of 5 over the minicomputer software formerly used. The hardw... View full abstract»

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  • A New Representation for Decimal Numbers

    Publication Year: 1977, Page(s):1286 - 1288
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    A new representation for decimal numbers is proposed. It uses a mixture of positive and negative radixes to ensure that the maximum value of a four bit decimal digit is 9. This eliminates the more complex carry generation process required in BCD addition. View full abstract»

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  • An Optimal Orthogonal Expansion for Classification of Patterns

    Publication Year: 1977, Page(s):1288 - 1290
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB)

    In this correspondence, the Karhunen-Loève expansion is generalized for multiclass classification and some optimal properties desirable for the feature extraction process are proved. This expansion is based upon a weighted covariance matrix with the interclass and intraclass distances. View full abstract»

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  • Algorithms in Numerical Geometry System

    Publication Year: 1977, Page(s):1290 - 1292
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (675 KB)

    Three papers [3],[9],[11] have described a numerical geometry system jointly implemented by IBM and Teledyne-Ryan Aeronautical in San Diego. They devoted attention specifically to the overall program structure and system capabilities. The present paper discusses this system from a point of view at the mathematical and algorithmic levels. View full abstract»

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  • Hardware Verification

    Publication Year: 1977, Page(s):1292 - 1294
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (705 KB)

    The need for verification of hardware designs is particularly important for large-scale-integration technologies because of the great cost, in time and money, for engineering changes. This correspondence describes an efficient means for determining the equivalence of a behavioral, high-level, i.e., flowchart, definition of the design and a detailed regular logic design. It may be used between comp... View full abstract»

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  • Synthesis of Multithreshold Tree Networks

    Publication Year: 1977, Page(s):1294 - 1297
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (724 KB)

    -A multithreshold network realizes a multithreshold logic function of an equivalent analog excitation e which in turn could be realized by a weighted input network of Boolean variables. This correspondence presents the synthesis of multithreshold tree networks with conventional single-threshold elements. The maximum number of thresholds realized by the tree network is derived by using the graphica... View full abstract»

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  • Synthesis of Multiple-Valued Logic Networks Based on Tree-Type Universal Logic Module

    Publication Year: 1977, Page(s):1297 - 1302
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1211 KB)

    This correspondence presents a theoretical study on the synthesis of multiple-valued logic networks based on tree-type universal logic modules (T-ULM's). The mathematical notation of T-ULM is introduced. On the basis of the mathematical properties, an algorithm for synthesizing an arbitrary logic function of n variables with a smaller number of modules is presented. In this algorithm, only true an... View full abstract»

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  • Seniority Logic: A Logic for a Committee Machine

    Publication Year: 1977, Page(s):1302 - 1306
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1060 KB)

    A logic for a committee of perceptrons, called seniority logic, and a local adjustment algorithm for training a seniority committee are described. Like a majority committee, a seniority committee has the capacity to solve any two-class problem in which the classes are disjoint. Unlike a majority committee, a seniority committee may have members added during training, and a seniority committee is f... View full abstract»

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  • An Algorithm for Constrained Maximization of the Trace of a Matrix

    Publication Year: 1977, Page(s):1306 - 1308
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (538 KB)

    The "trace" of a rectangular matrix is defined as the trace of a square matrix obtained by appending null rows (or columns) at the bottom (or right) end. The problem of maximizing the trace of a matrix, by permutations and mergers of rows and columns with constraints on the resulting size of the matrix, is of interest in comparison of maps and image-change detection. This correspondence presents a... View full abstract»

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  • 1977 Index IEEE Transactions on Computers Vol. C-26

    Publication Year: 1977, Page(s): 1308
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    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org