IEEE Transactions on Computers

Issue 6 • June 1976

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  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1976, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1976, Page(s): c2
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  • Fault-Tolerant Computing: A Introduction

    Publication Year: 1976, Page(s):553 - 556
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2197 KB)

    THE field of fault-tolerant computing is concerned with the analysis, design, verification, and diagnosis of computing systems that are subject to faults. A "computing system," in this general context, can be a hardware system, a software system, or a computer which includes both hardware and internal software. A "fault" can reside in either hardware or software and can occur in the process of des... View full abstract»

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  • Implementation of an Experimental Fault-Tolerant Memory System

    Publication Year: 1976, Page(s):557 - 568
    Cited by:  Papers (31)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3353 KB)

    The experimental fault-tolerant memory system described in this paper has been designed to enable the modular addition of spares, to validate the theoretical fault-secure and self-testing properties of the translator/corrector, to provide a basis for experiments using the new testing and correction processes for recovery, and to determine the practicality of such systems. The hardware design and i... View full abstract»

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  • A Highly Efficient Redundancy Scheme: Self-Purging Redundancy

    Publication Year: 1976, Page(s):569 - 578
    Cited by:  Papers (48)  |  Patents (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3147 KB)

    The goals of this paper are to present an efficient redundancy scheme for highly reliable systems, to give a method to compute the exact reliability of such systems and to compare this scheme with other redundancy schemes. This redundancy scheme is self-purging redundancy, a scheme that uses a threshold voter and that purges the failed modules. Switches for self-purging systems are extremely simpl... View full abstract»

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  • Computation-Based Reliability Analysis

    Publication Year: 1976, Page(s):578 - 584
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2614 KB)

    A reliability analysis method for computing systems is considered in which the underlying criteria for "success" are based on the computations the system must perform in the use environment. Beginning with a general model of a "computer with faults," intermediate concepts of a "tolerance relation" and an "environment space" are introduced which account for the computational needs of the user and t... View full abstract»

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  • A Theory of Diagnosability of Digital Systems

    Publication Year: 1976, Page(s):585 - 593
    Cited by:  Papers (148)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2951 KB)

    The problem of automatic fault diagnosis of systems decomposed into a number of interconnected units is considered by using a simplified version of the diagnostic model introduced by Preparata et al. The model used in this paper is supposed to be a realistic representation of systems where each unit has a considerable computational capability. For any system of n units whose set of testing links i... View full abstract»

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  • A Module-Level Testing Approach for Combinational Networks

    Publication Year: 1976, Page(s):594 - 604
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3354 KB)

    A module-level testing approach for combinational networks which employs hardware modification and a simplified test generation procedure is described. The approach is based on a directed graph model for the network derived at the module level. The objectives of the approach are to deal with testing directly at the module level, to use cataloged tests for the modules in the network environment, an... View full abstract»

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  • Truth-Table Verification of an Iterative Logic Array

    Publication Year: 1976, Page(s):605 - 613
    Cited by:  Papers (46)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2609 KB)

    This paper studies the problem of fault detection in iterative logic arrays (ILA's) made up of combinational cells arranged in a one-dimensional configuration with only one direction for signal propagation. It is assumed that a fault can change the behavior of the basic cell of the array in an arbitrary way, as long as the cell remains a combinational circuit. It is further assumed that any number... View full abstract»

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  • Transition Count Testing of Combinational Logic Circuits

    Publication Year: 1976, Page(s):613 - 620
    Cited by:  Papers (90)  |  Patents (40)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3778 KB)

    Logic circuits are usually tested by applying a sequence of input patterns S to the circuit under test and comparing the observed response sequence R bit by bit to the expected response Ro. The transition count (TC) of R, denoted c(R), is the number of times the signals forming R change value. In TC testing c(R) is recorded rather than R. A fault is detected if the observed TC c(R) differs from th... View full abstract»

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  • A Logic System for Fault Test Generation

    Publication Year: 1976, Page(s):620 - 630
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3981 KB)

    This paper describes a logic system specifically designed for fault test generation. The system allows the user to impose a set of initial constraints on the elements of a logic network by indicating those values which an element may (or may not) assume for the test under consideration. He can be as vague or as specific as he wants in imposing these constraints. A set of logic tables is then used ... View full abstract»

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  • A Nine-Valued Circuit Model for Test Generation

    Publication Year: 1976, Page(s):630 - 636
    Cited by:  Papers (121)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3280 KB)

    A nine-valued circuit model for test generation is introduced which takes care of multiple and repeated effects of a fault in sequential circuits. Using this model test sequences can be determined which allow multiple and repeated effects of faults on the internal state of a sequential circuit. Thus valid test sequences are derived where other known procedures, like the D-algorithm, do not find an... View full abstract»

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  • Fail-Safe Asynchronous Machines with Multiple-Input Changes

    Publication Year: 1976, Page(s):637 - 642
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (955 KB)

    Several synthesis methods for fail-safe asynchronous sequential machines have been reported recently. All of these methods solve the race problem by using noncritical race state assignments. This approach generally results in large number of state variables, relatively complicated design, and the limitation of single-input change. View full abstract»

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  • A Double Track Error-Correction Code for Magnetic Tape

    Publication Year: 1976, Page(s):642 - 645
    Cited by:  Papers (11)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (749 KB)

    An error-correction code, presented here, uses two redundant tracks and one redundant character which are formed from the askew and the vertical redundancy check (AVRC) bits. The error-correction capability of this code is the same as for the ORC Patel and Hong's code, but the encoded codeblock dimension is not subject to constraints. View full abstract»

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  • Processor Testability and Design Consequences

    Publication Year: 1976, Page(s):645 - 652
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1392 KB)

    Our purpose is to define a methodology for writing (micro) programs to test CPU's for which no or few test facilities are available. View full abstract»

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  • Recursion and Testing of Combinational Circuits

    Publication Year: 1976, Page(s):652 - 654
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (633 KB)

    This correspondence shows how recursion can be used to simplify testing of combinational circuits. Necessary and sufficient conditions for testing simple iterative arrays (one-dimensional) with a fixed number of tests (independent of the number of cells) are given. Multiple faults and diagnosis in such circuits are also studied. The extension of the concept of simple iteration to complex iteration... View full abstract»

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  • The Error Latency of a Fault in a Sequential Digital Circuit

    Publication Year: 1976, Page(s):655 - 659
    Cited by:  Papers (55)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1146 KB)

    In digital circuits there is typically a delay between the occurrence of a fault and the first error in the output. This delay is the error latency of the fault. A model to characterize the error latency of a fault in a sequential circuit is presented. View full abstract»

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  • About Random Fault Detection of Combinational Networks

    Publication Year: 1976, Page(s):659 - 664
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1176 KB)

    Fault detection by applying a random input sequence simultaneously to a network under test and to a reference network is conside-red. A distinction between testing quality and detection quality is given. The detection surface is introduced as a characteristic parameter of a combinational network. The results are applied to TTL combinational circuits. View full abstract»

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  • On Monte Carlo Testing of Logic Tree Networks

    Publication Year: 1976, Page(s):664 - 667
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (612 KB)

    It is shown that by a proper selection of the probabilities of 0 and 1 at the inputs, the efficiency of random test generation can be improved. This correspondence includes some results describing the testing of actual logic networks used in a computer. View full abstract»

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  • 1975 List of Reviewers

    Publication Year: 1976, Page(s):668 - 672
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  • IEEE Computer Society Publications

    Publication Year: 1976, Page(s): 672
    Request permission for commercial reuse | PDF file iconPDF (138 KB)
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  • IEEE Computer Society Membership & Publications

    Publication Year: 1976, Page(s): 672
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org