By Topic

Design & Test of Computers, IEEE

Issue 1 • Date March 1992

Filter Results

Displaying Results 1 - 7 of 7
  • Techniques for synthesis of analog integrated circuits

    Publication Year: 1992 , Page(s): 8 - 18
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (967 KB)  

    The CAD tools that have been developed for automated analog synthesis are reviewed. The synthesis process is described. The major techniques employed by the tools are examined. They are knowledge-based hierarchical design, analytic design, and placement/routing. Critical design issues are identified. It is shown how the technique discussed could be combined in a comprehensive framework supporting design from specification to physical layout.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fault diagnosis in analog circuits using element modulation

    Publication Year: 1992 , Page(s): 19 - 29
    Cited by:  Papers (17)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (828 KB)  

    Analog fault diagnostic methods are reviewed. A branch fault-diagnosis technique that requires a single excitation source at one test frequency is introduced. The technique lets users construct linearly independent branch-diagnosis equations by modulating selected network elements. An example of the technique applied to a two-stage amplifier is given.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analog circuit fault diagnosis based on sensitivity computation and functional testing

    Publication Year: 1992 , Page(s): 30 - 39
    Cited by:  Papers (80)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (785 KB)  

    An approach based on functional testing and on sensitivity calculation of many output parameters for diagnosis of defective elements in analog circuits is presented. A sensitivity matrix that gives the relation between the deviation of output parameters and the deviation of defective components in a circuit forms the basis of the test equations. Diverse types of measurement help improve the diagnostic resolution. Experimental results are presented to clarify the algorithm and prove its efficiency in a practical case.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • System testability assessment for integrated diagnostics

    Publication Year: 1992 , Page(s): 40 - 54
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1195 KB)  

    Techniques for analyzing the testability of a system are presented. They are based on an information flow model detailed by the authors previously (see ibid., vol.8, no.4, p.12-25, (1991)). The techniques identify testability problems involving ambiguity, feedback, the test set, and multiple failures. The overall concern is with the ability to diagnose failures as part of an overall maintenance architecture.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Noncontact testing of circuits via a laser-induced plasma electrical pathway

    Publication Year: 1992 , Page(s): 55 - 63
    Cited by:  Papers (4)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (710 KB)  

    Systems using the three most popular probes applied to functional electrical testing, mechanical, electron beam, and laser, are reviewed. A system of noncontact testing that uses a laser-induced plasma 'switch' to provide the electrical pathway for AD and DC measurements on printed wiring boards is presented. With this technique, a DC resistance discrimination of less than 10 Omega and distortion-free AC measurements of a 2.5-MHz oscillator signal were achieved. These results are presented and evaluated.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Advanced fault collapsing (logic circuits testing)

    Publication Year: 1992 , Page(s): 64 - 71
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (613 KB)  

    The partitioning of faults into equivalence classes so that only one representative fault per class must be explicitly considered in fault simulation and test generation, called fault collapsing, is addressed. Two types of equivalence, which are relevant to the work reported, are summarized. New theorems on fault equivalence and dominance, forming the basis of an algorithm that collapses all the structurally equivalent faults in a circuit, plus many of the functionally equivalent faults, are presented. Application of the algorithm to a set of benchmark circuits establishes that identification of functionally equivalent faults is feasible, and that, in some cases, they are a large fraction of the faults in a circuit. The collapsing algorithm applies not only to combinational designs but to synchronous sequential circuits as well.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Empirical failure analysis and validation of fault models in CMOS VLSI circuits

    Publication Year: 1992 , Page(s): 72 - 83
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1040 KB)  

    A way to empirically validate fault models and to measure the effectiveness of test sets based on the targeted fault models is described. The authors use automated fault diagnosis of test circuits representative of the circuits being studied and of the fabrication process, cell libraries, and CAD tools used in their development. The design and fabrication of a test chip using an experimental CMOS, 1.5- mu m double-layer metal process are discussed.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty