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Device and Materials Reliability, IEEE Transactions on

Issue 2 • Date June 2006

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Displaying Results 1 - 25 of 39
  • [Front cover]

    Publication Year: 2006 , Page(s): c1
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    Freely Available from IEEE
  • IEEE Transactions on Device and Materials Reliability publication information

    Publication Year: 2006 , Page(s): c2
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  • Table of contents

    Publication Year: 2006 , Page(s): 113 - 114
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  • Introduction to the Special Issue on the 2005 International Integrated Reliability Workshop

    Publication Year: 2006 , Page(s): 115 - 116
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  • Observations of NBTI-induced atomic-scale defects

    Publication Year: 2006 , Page(s): 117 - 122
    Cited by:  Papers (12)
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    A combination of MOSFET gate-controlled diode measurements and a very sensitive electron spin resonance technique called spin-dependent recombination was utilized to observe and identify defect centers generated by a negative bias temperature stress in fully processed SiO 2-based pMOSFETs. In SiO2 devices, the defects include two Si/SiO2 interface silicon dangling bond centers (Pb0 and Pb1) and may also include an oxide silicon dangling bond center (E'). The observations indicate that both P b0 and Pb1 defects play major roles in these SiO 2-based devices and suggest that E' centers could play an important role View full abstract»

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  • Electron trap generation in high-/spl kappa/ gate stacks by constant voltage stress

    Publication Year: 2006 , Page(s): 123 - 131
    Cited by:  Papers (23)
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    Positive bias constant voltage stress combined with charge pumping (CP) measurements were applied to study trap generation phenomena in SiO 2/HfO2/TiN stacks. Using gate stacks with varying thicknesses of the interfacial SiO2 layer (IL) or high-kappa layer and analysis for frequency-dependent CP data developed to address trap depth profiling, the authors have determined that the defect generation in the stress voltage range of practical importance occurs primarily within the IL on as-grown "precursor" defects most likely caused by the overlaying HfO2 layer. The generated traps can be passivated by a forming gas or nitrogen (N2 ) anneal, whereas a postanneal stress reactivates these defects. The results obtained identify the IL as one of the major targets for reliability improvement of high-kappa stacks View full abstract»

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  • Origin of Vt instabilities in high-k dielectrics Jahn-Teller effect or oxygen vacancies

    Publication Year: 2006 , Page(s): 132 - 135
    Cited by:  Papers (4)
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    In this paper, an analysis of the trapping in high- dielectrics and its origin is given. It is found that the defect is consistent with oxygen vacancies in monoclinic hafnia. Finally, guidelines are proposed to reduce these instabilities View full abstract»

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  • Stacked dual-oxide MOS energy band diagram visual representation program (IRW student paper)

    Publication Year: 2006 , Page(s): 136 - 145
    Cited by:  Papers (7)
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    Energy band diagrams for MOS devices are essential for understanding device performance and reliability. Introduction of high-k gate stacks with a silicon dioxide (SiO2) interfacial layer requires an even greater understanding of the energy band behavior. A program that quickly determines the band diagrams based on a simple analytical model was created. It is used to explore the behavior of various oxide stacks with the ability to easily vary important parameters like oxide material, electron affinity, bandgap, dielectric constant, and thickness. The usefulness of this program to predict potential reliability issues is also demonstrated View full abstract»

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  • Design for ASIC reliability for low-temperature applications

    Publication Year: 2006 , Page(s): 146 - 153
    Cited by:  Papers (7)
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    A design for reliability methodology has been developed for electronics for low-temperature applications. A hot carrier aging (HCA) lifetime projection model is proposed to take into account the HCA impact on technology, analysis of parametric degradation versus critical circuit path degradation, transistor bias profile, transistor substrate current profile, and operating temperature profile. The most applicable transistor size can be determined in order to meet the reliability requirements of the electronics operating under low temperatures. This methodology and approach can also be applied to other transistor-level failure and/or degradation mechanisms for applications with varying temperature ranges View full abstract»

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  • A new degradation mode for heterojunction bipolar transistors under reverse-bias stress

    Publication Year: 2006 , Page(s): 154 - 162
    Cited by:  Papers (1)
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    A new degradation behavior for heterojunction bipolar transistors under reverse base-emitter junction stress is presented and discussed. Hot carrier injection triggered a correlated decrease of both the base and collector-currents in the first stress-time steps. Both experiments and simulations show that this degradation is linked to the stress-induced suppression of initially present excess ideal components for both currents View full abstract»

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  • Via-depletion electromigration in copper interconnects

    Publication Year: 2006 , Page(s): 163 - 168
    Cited by:  Papers (5)
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    Via-depletion electromigration was studied under a number of conditions in a 65-nm technology. Observed failure distributions were either single mode or bimodal, depending on the structural configuration. The distribution and the time to fail for the early-fail mode of the bimodal distributions varied with linewidth, via redundancy, and via current density. Additionally, it was observed that for bimodal failure distributions, the length of the extension of the line past the via determined the fraction of early fails in the via. The bimodal behavior was suppressed by optimization of the via liner deposition process View full abstract»

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  • Moisture influence on porous low-k reliability

    Publication Year: 2006 , Page(s): 169 - 174
    Cited by:  Papers (5)  |  Patents (1)
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    In this paper, the impact of moisture on the reliability of porous low-k materials has been investigated. It was found that moisture uptake is higher for more porous SiOC low-k materials, and its presence inside the low-k has a strong impact on the dielectric reliability. It has been demonstrated that by eliminating moisture, the leakage current can be significantly decreased; in addition, higher breakdown electric fields and longer dielectric lifetimes can be achieved. Therefore, integration of porous low-k materials requires maximum attention to prevent moisture uptake at each step during integration; in addition, the passivation layers need to be perfectly hermetic in order to maintain good dielectric reliability View full abstract»

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  • Stress-induced electromigration backflow effect in copper interconnects

    Publication Year: 2006 , Page(s): 175 - 180
    Cited by:  Papers (7)  |  Patents (1)
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    The electromigration threshold in copper interconnect is reported in this paper. The critical product (jL)c is first determined for copper oxide interconnects with temperature ranging from 250degC to 350degC from package-level experiments. It is shown that the product does not significantly change in this temperature range. Then, (jL)c was extracted for copper low-k dielectric (k=2.8) interconnects at 350degC. A larger value than that for oxide dielectric was found. Finally, a correlation between the n values from Black's model and with jL conditions was established for both dielectrics View full abstract»

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  • Introduction to the Special Issue on the IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits

    Publication Year: 2006 , Page(s): 181
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  • Transmission EELS attachment for SEM

    Publication Year: 2006 , Page(s): 182 - 185
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (274 KB) |  | HTML iconHTML  

    At the present transmission, an electron energy-loss spectrum (EELS) analysis is only carried out in transmission electron microscopes, such as the transmission electron microscopes (TEMs) or the Scanning Transmission Electron Microscopes (STEMs). Although the elemental analysis can be done in the scanning electron microscopes (SEMs) with an energy dispersive X-ray (EDX), its energy resolution is typically limited between 100-150 eV, nearly two orders of the magnitude larger than the energy resolution of the EELS in the TEMs/STEMs. This paper presents an EELS attachment for the conventional SEMs. K edge and the EELS low-loss spectrum of a thin amorphous carbon film are obtained in a Philips XL30 field emission SEM. The EELS attachment has the capability of acquiring structural information and 4 eV energy resolution at 30-keV primary beam energy View full abstract»

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  • Application of conductive AFM on the electrical characterization of single-bit marginal failure

    Publication Year: 2006 , Page(s): 186 - 189
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    The challenge to determine the failure mechanism in submicrometer devices has been increasing with transitions in technological processes. Determining the failure mechanism and finding the associated physical defect have become extremely difficult, if not impossible, due to the increased complexity in architecture and the extremely large number of transistors in ICs. In this investigation, the efficiency and the success rate of using conductive atomic force microscope (cAFM) in the localization of defects in 90-nm devices are shown. How the method was utilized to obtain full electrical data on a single-bit failure using the I-V curve sweep mode and how cAFM can be a suitable alternative to the passive voltage contrast method and in-chamber pico-probing were also demonstrated View full abstract»

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  • Postbreakdown current in MOS structures: extraction of parameters using the Integral difference function method

    Publication Year: 2006 , Page(s): 190 - 196
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (307 KB) |  | HTML iconHTML  

    This paper deals with the extraction of parameters and simulation of the postbreakdown leakage current in pMOS devices with ultrathin oxides. The model considered is based on the generalized diode equation, i.e., a diode-like equation with series resistance. The current-voltage (I-V) characteristic can be expressed in a closed-form expression, which makes it is suitable for circuit simulation environments. Model parameters are extracted using the integral difference function (IDF) method. Because the exact expression for the I-V characteristic is used for computing the IDF, the method does not involve any kind of approximation. The effect of including a nonlinear correction term to the voltage drop across the structure is also discussed View full abstract»

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  • Stress migration lifetime for Cu interconnects with CoWP-only cap

    Publication Year: 2006 , Page(s): 197 - 202
    Cited by:  Papers (1)
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    Stress migration lifetime is characterized for a CoWP-only cap process (i.e., no dielectric cap) and a CoWP + SiN cap process. For the CoWP-only process, the stress migration lifetime depends on the CoWP thickness. In order to achieve a long stress migration lifetime, the CoWP must be sufficiently thick to protect the Cu during the via etch and strip processes. The data suggests that CoWP removal is enhanced beneath partially landed vias, resulting in reduced stress migration lifetime View full abstract»

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  • Imaging and dopant profiling of silicon carbide devices by secondary electron dopant contrast

    Publication Year: 2006 , Page(s): 203 - 212
    Cited by:  Papers (2)
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    In this paper, the secondary electron dopant contrast in scanning electron microscopy is proposed as the method of choice for dopant imaging and profiling in silicon carbide devices. After reviewing the physical principles of the signal generation, the impact on the image quality of relevant factors such as experimental conditions, surface effects, and sample preparation is investigated. The quantitative capabilities of this technique are compared with the performance of the most advanced scanning probe methods. Particular attention is devoted to the quantitative delineation of electrical junctions and the two-dimensional dopant profiling of complex structures View full abstract»

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  • Surface electrostatic damage by microprocess robotic machines: diagnosis and reliability, process auditing, and remedies

    Publication Year: 2006 , Page(s): 213 - 220
    Cited by:  Papers (3)
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    Electrostatic discharge (ESD) is generally known as a discharge phenomena via device pins. Many precautions have been taken against ESD, mostly considering workplace protection, pad protection structures. However, electrostatic events, originating from robotic semiconductor wafer- and device-processing seems at least a problem of similar severeness, which has not been considered enough, yet. This paper describes electrostatic mechanisms in most common assembly process tools, how to do diagnostics on devices and tool auditing. Auditing experiences are listed and hints how to improve tool-related ESD are described View full abstract»

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  • Safe operating area of GaAs MESFET for nonlinear applications

    Publication Year: 2006 , Page(s): 221 - 227
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    This paper provides a new approach to evaluate the transistor safe operating area for a nonlinear operation in the overdrive operating conditions. This approach has been implemented for a MESFET technology. The methodology consists in performing ON-state and OFF-state accelerated DC step stresses for bias conditions, which can be reached by VDS and VGS sweeps in the overdrive operating conditions. Hence, the results of an RF ageing test performed in nonlinear conditions have confirmed the methodology used in this paper View full abstract»

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  • Improvement of aging simulation of electronic circuits using behavioral modeling

    Publication Year: 2006 , Page(s): 228 - 234
    Cited by:  Papers (7)  |  Patents (1)
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    This paper presents an original method of analog circuits aging simulation. This method is based on a behavioral modelling of circuits that includes the effects of degradations on circuit parameters, on the basis of transistors aging. The efficiency of the method is demonstrated in the case of hot carriers degradation in an amplifier View full abstract»

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  • SRAM circuit-failure modeling and reliability simulation with SPICE

    Publication Year: 2006 , Page(s): 235 - 246
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1005 KB) |  | HTML iconHTML  

    Based on some new accelerated lifetime models and failure equivalent circuit modeling techniques for the common semiconductor wear out mechanisms, simulation program with integrated circuit emphasis (SPICE) can be used to characterize CMOS VLSI circuit failure behaviors and perform reliability simulation. This paper used a simple SRAM circuit as an example to demonstrate how to apply SPICE to circuit reliability modeling, simulation, analysis, and design. The SRAM circuit, implemented with a commercial 0.25-mum technology, consists of functional blocks of 1-bit six-transistor cell, precharge, read/write control, and sense amplifier. The SRAM operation sequence of "write 0, read 0, write 1, read 1" was first simulated in SPICE to obtain the terminal voltage and current stress profiles of each transistor. Then, normalized lifetimes of all transistors in terms of each failure mechanism were calculated with the corresponding accelerated lifetime models. These lifetime values were sorted to single out the most damaged transistors. Finally, the selected transistors were substituted with failure equivalent circuit models, and SPICE simulations were performed again to characterize the circuit performance, functionality, and failure behaviors. The simulation shows that the 0.25-mum technology, hot-carrier injection (HCI), and time-dependent dielectric breakdown (TDDB) had significant effects on SRAM-cell stability and voltage-transfer characteristics, while negative bias temperature instability (NBTI) mainly degraded the cell transition speed when the cell state flipped. This illustrative SRAM simulation work proves that, with SPICE and the failure equivalent circuit models, circuit designers can better understand the damage effects of HCI/TDDB/NBTI on the circuit operation, quickly estimate the circuit lifetime, make appropriate performance/reliability tradeoffs, and formulate practical design guidelines to improve the circuit reliability View full abstract»

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  • A new SPICE reliability simulation method for deep submicrometer CMOS VLSI circuits

    Publication Year: 2006 , Page(s): 247 - 257
    Cited by:  Papers (20)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB) |  | HTML iconHTML  

    CMOS very large scale integration (VLSI) circuit reliability modeling and simulation have attracted an intense research interest in the last two decades, and as a result, almost all IC reliability simulation tools now try to incrementally characterize the wearout mechanisms of aged devices in iterative ways. These tools are able to accurately simulate the device's wearout process and predict its impact on the circuit performance. Nevertheless, an excessive simulation time, a tedious device testing work, and a complex parameter extraction process often limit the popularity of these tools in the product design and fabrication stages. In this paper, a new simulation program with integrated circuits emphasis (SPICE) reliability simulation method is developed, which shifts the focus of the reliability analysis from the device wearout to the circuit functionality. A set of accelerated lifetime models and failure equivalent circuit models have been proposed for the most common silicon intrinsic wearout mechanisms, including hot-carrier injection, time-dependent dielectric breakdown, and negative bias temperature instability. The accelerated lifetime models help to identify the most degraded transistors in a circuit in terms of the device's terminal voltage and current stress profiles. Then, the corresponding failure equivalent circuit models are incorporated into the circuit to substitute these identified transistors. Finally, the SPICE simulation is performed again to check the circuit functionality and analyze the impact of the device wearout on the circuit operation. Device individual wearout effect is lumped into a very limited number of SPICE circuit elements within each failure equivalent circuit model, and the circuit performance degradation and functionality are determined by the magnitude of these additional circuit elements. In this new method, it is unnecessary to perform a large number of small-step iterative SPICE simulation process as other tools required t- - o obtain the accuracy. Therefore, the simulation time is obviously shortened. In addition, a reduced set of failure equivalent circuit model parameters, rather than a large number of device SPICE parameters, need to be accurately characterized at each interim wearout process. Thus, the device testing and parameter extraction work are also significantly simplified. These advantages will allow the circuit designers to perform a quick and efficient circuit reliability analysis and to develop practical guidelines for reliable electronic designs View full abstract»

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  • Electronic system reliability: collating prediction models

    Publication Year: 2006 , Page(s): 258 - 265
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (151 KB) |  | HTML iconHTML  

    This paper summarizes research done in the area of electronic system reliability and assesses the approaches used in the calculation of electronic system failure rates. A detailed literature survey is conducted to investigate the various available reliability prediction models. The paper starts with a definition of reliability, briefly discusses various regions of system failure rate in time, justifies the role of reliability prediction methods, provides a historical overview, classifies the traditional models into easy to understand categories and discusses the advantages and disadvantage, reviews the key models that are currently in use, and compares the first and most widely used model (i.e., MIL-HDBK-217) with the most recently introduced model (i.e., PRISM) View full abstract»

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Aims & Scope

IEEE Transactions on Device and Materials Reliability is published quarterly. It provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the manufacture of these devices; and the interfaces and surfaces of these materials.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Anthony S. Oates
Taiwan Semiconductor Mfg Co.