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IEEE Transactions on Computers

Issue 5 • Date May 1975

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Displaying Results 1 - 24 of 24
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1975, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1975, Page(s): c2
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  • Fault-Tolerant Computing: An Introduction and a Perspective

    Publication Year: 1975, Page(s):457 - 460
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2184 KB)

    FAULT-TOLERANT computing has been defined as "the ability to execute specified algorithms correctly regardless of hardware failures, total system flaws, or program fallacies" [1]. To the extent that a system falls short of meeting the requirements of this definition, it can be labeled a partially fault-tolerant system [2]. Thus the definition of fault-tolerant computing provides a standard against... View full abstract»

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  • An Approach to the Diagnosis of Intermittent Faults

    Publication Year: 1975, Page(s):461 - 467
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2440 KB)

    A procedure for the diagnosis of intermittent faults in combinational circuits is suggested. This procedure employs a probabilistic model for intermittent failures and presumes that a detection experiment has been run. The circuit is assumed to be irredundant and to possess a single fault out of n possible ones. The approach suggested is based on the repeated application of tests that test for the... View full abstract»

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  • On-Line Diagnosis of Unrestricted Faults

    Publication Year: 1975, Page(s):468 - 475
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2752 KB)

    A formal model for the study of on-line diagnosis is introduced and used to investigate the diagnosis of unrestricted faults. Within this model a fault of a system S is considered to be a transformation of S into another system S' at some time r. The resulting faulty system is taken to be the system which looks like S up to time r and like S' thereafter. Notions of fault tolerance and error are de... View full abstract»

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  • Fault Masking in Combinational Logic Circuits

    Publication Year: 1975, Page(s):476 - 482
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2160 KB)

    An important problem in fault detection is to verify whether a single-fault test set is able to detect all multiple-faults. This paper provides a solution to the above problem. It is known that a test set derived for the detection of some fault may fail this purpose in the presence of an additional fault. This phenomenon is called masking among faults, and is of great importance in the derivation ... View full abstract»

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  • A Totally Self-Checking Checker Design for the Detection of Errors in Periodic Signals

    Publication Year: 1975, Page(s):483 - 489
    Cited by:  Papers (11)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2616 KB)

    Periodic signals have a known behavior, and deviations in their waveforms may indicate failures in the signal source. Monitoring these signals can be a valuable technique in detecting both hardware and software failures in a computer. Schemes previously used to check for errors in these signals are reviewed and evaluated. These circuits, however, share a common weakness in that they are susceptibl... View full abstract»

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  • An Advanced Fault Isolation System for Digital Logic

    Publication Year: 1975, Page(s):489 - 497
    Cited by:  Papers (57)  |  Patents (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2992 KB)

    Advances in integrated circuit technology are decreasing acquisition cost per function of digital hardware while system software costs are increasing. The hardware advances allow practical implementation of more sophisticated and complex systems which have fewer components, but which may present severe test and maintenance problems due to their complexity. As a result, the use of built-in test (BI... View full abstract»

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  • The Architectural Elements of a Symmetric Fault-Tolerant Multiprocessor

    Publication Year: 1975, Page(s):498 - 505
    Cited by:  Papers (11)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2864 KB)

    A hybrid-redundant multiprocessor is proposed in which each processing unit and each memory module is triplicated for purposes of error detection and momentary error masking Reconfiguration allows spare units to replace failed units and allows surviving units to regroup after spares have been exhausted. An arbitrary number of processing units and memory modules can be accommodated. A hybrid-redund... View full abstract»

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  • A Damage- and Fault-Tolerant Input/Output Network

    Publication Year: 1975, Page(s):505 - 512
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2976 KB)

    A damage-and fault-tolerant input/output (I/O) network is presented as an alternative to I/O buses. Such a network differs most significantly from telecommunications networks (such as the ARPA net) in that the nodes of this net are very simple and do not perform such tasks as message or packet switching and buffering. Data routing through the net is directly controlled by a centralized processor w... View full abstract»

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  • Orthogonal Latin Square Configuration for LSI Memory Yield and Reliability Enhancement

    Publication Year: 1975, Page(s):512 - 516
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1848 KB)

    When errors occur which exceed the correction capability of an error correcting code, the only recourse to restore the original memory function is to physically replace the failed entity. In this paper the authors propose an automatic reconfiguration technique which uses the concept of address skewing to disperse such multiple errors into correctable errors. No additional redundancy other than tha... View full abstract»

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  • A Reliability Model for Gracefully Degrading and Standby-Sparing Systems

    Publication Year: 1975, Page(s):517 - 525
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2808 KB)

    A model for analyzing the reliability of gracefully degrading and standby-sparing computer systems is developed. The basis of the model is the identification of four distinct causes of crashes: time-domain multiple faults, resource exhaustion, space-domain multiple faults, and solitary faults. Expressions are developed for each of these crash-causing mechanisms and for their interrelationship. The... View full abstract»

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  • Reliability Modeling of Compensating Module Failures in Majority Voted Redundancy

    Publication Year: 1975, Page(s):525 - 533
    Cited by:  Papers (24)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3880 KB)

    The classical reliability model for N-modular redundancy (NMR) assumes the network to be failed when a majority of modules which drive the same voter fail. It has long been known that this model is pessimistic since there are instances, termed compensating module failures, where a majority of the modules fail but the network is nonfailed. A different module reliability model based on lead reliabil... View full abstract»

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  • The Probability of a Correct Output from a Combinational Circuit

    Publication Year: 1975, Page(s):534 - 544
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2880 KB)

    The paper discusses two methods to evaluate the signal reliability of the output of logical circuits. It is known that faults present in a circuit will not always cause the output of the circuit to be incorrect. Given the probability of faults occurring in the circuit and the probabilities of the input combinations, it is possible to determine the likelihood of the output being correct. The signal... View full abstract»

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  • Some Problems in Certifying Microprograms

    Publication Year: 1975, Page(s):545 - 553
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2784 KB)

    A hypothetical computer is described, and procedures are indicated for showing the correctness of its microprogram. The underlying method used is that of Birman [1]. However, the computer discussed has some realistic characteristics not shared by the machine treated in [1], and the details of the microcode validation are complicated by this fact. A formal technique for partitioning the proof is pr... View full abstract»

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  • Methodology for the Generation of Program Test Data

    Publication Year: 1975, Page(s):554 - 560
    Cited by:  Papers (46)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2792 KB)

    A methodology for generating program test data is described. The methodology is a model of the test data generation process and can be used to characterize the basic problems of test data generation. It is well defined and can be used to build an automatic test data generation system. View full abstract»

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  • A Method for Obtaining SPOOF's

    Publication Year: 1975, Page(s):560 - 562
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    A compatibility relationship on network paths is defined in such a way that the maximal compatibles are isomorphic to the products in the "structure and parity-observing output function" (SPOOF), a subscripted Boolean expression for the network output that uniquely specifies the network structure. For a given network, the path compatibility relations are easy to find, as are the maximal compatible... View full abstract»

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  • Diversified Test Methods for Local Control Units

    Publication Year: 1975, Page(s):562 - 567
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1192 KB)

    Two different test methods, specific to two control mechanisms in a logic network are presented. These methods, in fact, correspond to two levels of complexity and therefore to two kinds of hardware realizations. The main considerations will be the following. View full abstract»

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  • Design of Reliable Synchronous Sequential Circuits

    Publication Year: 1975, Page(s):567 - 570
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (912 KB)

    Fail-safe synchronous sequential machines produce safeside outputs when failures occur within the machine. This correspondence presents a procedure to design such machines using a modification of the on-set equation form originally presented by Tohma et al. [1] and later improved by Diaz et al. [2]. A systematic procedure for state assignment and next-state equation derivation, using partition the... View full abstract»

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  • Transient Failures in Triple Modular Redundancy Systems with Sequential Modules

    Publication Year: 1975, Page(s):570 - 573
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (912 KB)

    The effects of transient failures in sequential modules in systems using triple modular redundancy (TMR) cannot be neglected. A transient may place a sequential machine in an erroneous state, and the state may remain erroneous long after the transient has disappeared. We show that the state of a sequential machine can be restored after a transient if and only if the machine has a synchronizing seq... View full abstract»

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  • Analysis of Logic Circuits with Faults Using Input Signal Probabilities

    Publication Year: 1975, Page(s):573 - 578
    Cited by:  Papers (44)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1088 KB)

    A probabilistic treatment of general combinational networks has been developed. Using the notions of the probability of a signal and signal independence, algorithms have been presented to calculate the probability of the output of a logic circuit being 1. Simplifications to the algorithm result when sets of input probabilities are given the same value, and this process called bundling is described... View full abstract»

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  • A Combinatorial Solution to the Reliability of Interwoven Redundant Logic Networks

    Publication Year: 1975, Page(s):578 - 584
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (976 KB)

    A combinatorial procedure is given to calculate the reliability of an interwoven redundant logic network to any desired degree of accuracy. The procedure consists of enumerating combinations of gate failure which are tolerated by the redundant network, and is explained with reference to a quadded logic network. Since the exact reliability calculation might be too time consuming for large networks,... View full abstract»

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  • IEEE Computer Society Publications

    Publication Year: 1975, Page(s): 584-a
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  • IEEE Computer Society Membership & Publications

    Publication Year: 1975, Page(s): 584
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org