IEEE Transactions on Computers

Issue 7 • July 1974

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  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1974, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1974, Page(s): c2
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  • Fault-Tolerant Computing: An Introduction

    Publication Year: 1974, Page(s):649 - 650
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1368 KB)

    FAULT-TOLERANT computing has been defined as "the ability to execute specified algorithms correctly regardless of hardware failures, total system flows, or program fallacies" [1]. This definition of fault-tolerant computing leads directly to three major subdivisions [2]: View full abstract»

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  • Fault-Tolerant Asynchronous Sequential Machines

    Publication Year: 1974, Page(s):651 - 657
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1168 KB)

    A general design technique for achieving single fault-tolerant asynchronous sequential circuits is described. The design procedures apply over a large range of fault conditions and are extremely easy to use. Generally, less than three times the logic required for a single copy is needed to achieve single fault tolerance. In addition to fault tolerance, real time fault detection is easily achieved ... View full abstract»

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  • Partially Self-Checking Circuits and Their Use in Performing Logical Operations

    Publication Year: 1974, Page(s):658 - 666
    Cited by:  Papers (17)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2688 KB)

    A new class of circuits called "partially self-checking circuits" is described. These circuits have one mode of operation called secure mode in which every fault is tested in normal operation and no fault can cause an undetected error. They also have an insecure mode of operation in which undetected errors can occur; however, every fault that can cause an error in insecure mode is tested by some i... View full abstract»

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  • Fault-Tolerance of the Iterative Cell Array Switch for Hybrid Redundancy

    Publication Year: 1974, Page(s):667 - 681
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3376 KB)

    The technique of hybrid redundancy has been used to protect those portions of a digital system which have to be made ultrareliable. Siewiorek and McCluskey have presented a new switch design for hybrid redundancy which is shown to be of less complexity than other switch designs presented in the literature. View full abstract»

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  • An Algorithm for the Accurate Reliability Evaluation of Triple Modular Redundancy Networks

    Publication Year: 1974, Page(s):682 - 692
    Cited by:  Papers (38)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2912 KB)

    There are several instances where the classical method of triple-modular redundancy (TMR) reliability modeling may provide predictions which are inadequate. It is shown that for even simple networks such as those exhibiting fan-in and fan-out, classical methods may predict a reliability that is higher than or lower than the actual reliability. Furthermore, the classical method gives no hint as to ... View full abstract»

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  • An Organization for a Highly Survivable Memory

    Publication Year: 1974, Page(s):693 - 705
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3584 KB)

    A memory organization is considered for which a large number of faults can be tolerated at a low cost in redundancy. The primitive element in the memory is a large-scale integrated (LSI) chip that realizes a section of memory, b bits wide by y words long, together with an address decoder for the y words. The chips (including spares) are connected via a switching network so that the memory can be r... View full abstract»

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  • Fault Diagnosis as a Graph Coloring Problem

    Publication Year: 1974, Page(s):706 - 713
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2664 KB)

    A method is presented for converting problems in fault diagnosis into ones involving coloring (labeling) the nodes of a graph. It is shown that many concepts and results of graph theory have direct counterparts in fault diagnosis. Specific fault diagnosis problems examined include exercising tests, fanout free networks, test point insertion, sensitized paths, and fault test generation. A number of... View full abstract»

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  • Intermittent Faults: A Model and a Detection Procedure

    Publication Year: 1974, Page(s):713 - 719
    Cited by:  Papers (37)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2456 KB)

    Intermittent faults are those faults whose effects on the behavior of a system are present only part of the time. A probabilistic model for intermittent faults in digital circuits is suggested. A procedure for the detection of such faults in combinational circuits is proposed. The procedure employs the repeated application of tests that test for these faults as if their effects were permanent. The... View full abstract»

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  • Bridging and Stuck-At Faults

    Publication Year: 1974, Page(s):720 - 727
    Cited by:  Papers (153)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2840 KB)

    The commonly used stuck-at fault fails to model logic circuit shorts. Bridging faults are defined to model these circuit mal-functions. This model is based on wired logic which is a characteristic of many logic families such as resistor-transistor logic (RTL), diode transistor logic (DTL), emitter-coupled logic (ECL), etc. It does not apply to TTL circuits. The model also limits to fan-out-free le... View full abstract»

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  • Test Point Placement to Simplify Fault Detection

    Publication Year: 1974, Page(s):727 - 735
    Cited by:  Papers (65)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3680 KB)

    The problem of selecting test points to reduce the number of tests for fault detection in combinational logic networks is examined. A method is presented for labeling the lines of a network. Procedures are described for obtaining a minimal labeling, i.e., one corresponding to a minimal set of tests, for fanout-free circuits and for a restricted class of circuits with fanout. Using these procedures... View full abstract»

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  • A Method for the Realization of Fail-Safe Asynchronous Sequential Circuits

    Publication Year: 1974, Page(s):736 - 739
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (864 KB)

    The problem of the realization of fail-safe asynchronous sequential circuits was recently studied by Patterson and Sawin. This correspondence presents a different approach to the same subject which, in some cases, yield us simpler realization than those by the methods ever proposed, combining the notion of the ordered partition with Tracey's method for the state assignment of asynchronous sequenti... View full abstract»

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  • The Reliability Impact of Mission Abort Strategies on Redundant Flight Computer Systems

    Publication Year: 1974, Page(s):739 - 743
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1008 KB)

    This correspondence presents a reliability model for a redundant flight computer system with. standby sparing, taking into account various mission abort strategies. A mission rule to initiate a mission abort after a predetermined number of detected computer failures and to return to earth with the remaining computers is shown to result in: 1) little improvement of crew safety unless computer error... View full abstract»

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  • An Examination of Algebraic Test Generation Methods for Multiple Faults

    Publication Year: 1974, Page(s):743 - 745
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    A generalized test function (GTF) is derived that gives all tests for a multiple stuck-at fault in a combinational logic circuit. The GTF is then used as the basis for an examination of several algebraic test generation methods that have appeared in the literature. Deficiencies are found in some methods. View full abstract»

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  • Diagnosis of Short-Circuit Faults in Combinational Circuits

    Publication Year: 1974, Page(s):746 - 752
    Cited by:  Papers (35)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (904 KB)

    Most work on diagnosis of digital circuits has concentrated on the model of stuck-type faults. Although these faults are probably the most important class of faults, other types of faults do occur in practice and the occurrence of these other faults may affect the diagnosis of stuck-type faults. In this correspondence we consider the problems associated with detection of two other fault models, sh... View full abstract»

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  • IEEE Computer Society Publications

    Publication Year: 1974, Page(s): 752-a
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  • Compcon goes to Washington

    Publication Year: 1974, Page(s): 752
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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org