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Micro, IEEE

Issue 1 • Date Feb. 1992

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Displaying Results 1 - 5 of 5
  • The Scalable Coherent Interface and related standards projects

    Publication Year: 1992 , Page(s): 10 - 22
    Cited by:  Papers (58)  |  Patents (38)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1127 KB)  

    The Scalable Coherent Interface (SCI) (IEEE P1596), which provides bus services by transmitting packets on a collection of point-to-point unidirectional links, is described. Its protocols support cache coherence in a distributed shared-memory multiprocessor model, with message passing, I/O, and LAN communication taking place over fiber optic or wire links. Several ongoing SCI-related projects that apply the SCI technology to new areas or extend it to more difficult problems are also described. Future plans are sketched.<> View full abstract»

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  • Unix and the Am29000 microprocessor

    Publication Year: 1992 , Page(s): 23 - 31
    Cited by:  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (953 KB)  

    Features that make the AM29000 a good Unix host are examined. The discussion covers the C calling sequence, context switching, system calls, interrupt handling, memory access protection, cache support, multiprocessor Unix, floating-point support, and system costs.<> View full abstract»

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  • Hardware requirements for neural network pattern classifiers: a case study and implementation

    Publication Year: 1992 , Page(s): 32 - 40
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (773 KB)  

    A special-purpose chip, optimized for computational needs of neural networks and performing over 2000 multiplications and additions simultaneously, is described. Its data path is particularly suitable for the convolutional architectures typical in pattern classification networks but can also be configured for fully connected or feedback topologies. A development system permits rapid prototyping of new applications and analysis of the impact of the specialized hardware on system performance. The power and flexibility of the processor are demonstrated with a neural network for handwritten character recognition containing over 133000 connections.<> View full abstract»

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  • Experimentation with hypercube database engines

    Publication Year: 1992 , Page(s): 42 - 56
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1334 KB)  

    Using Intel's iPSC/2 hypercube, the authors measured the relationship between packet size, method of clustering messages, and internode traffic on the total sustained communication bandwidth. Having measured the costs associated with internode communication, they then analyzed duplicate removal algorithms. They also studied the effects of nonuniformly distributed attribute values and tuples across processors on three proposed duplicate removal algorithms. They chose algorithms to represent the several available in the literature and then evaluated the output collection time. The authors present a brief overview of the iPSC/2's hypercube message-passing system and discuss the results of their experimentation and analysis.<> View full abstract»

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  • Conformance testing of VMEbus and Multibus II products

    Publication Year: 1992 , Page(s): 57 - 64
    Cited by:  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (828 KB)  

    A system for testing VMEbus and Multibus II products is described. The system is mainly automated to reduce costs and ensure impartiality. A test campaign is explained in the sense of a walk through the test system, in the way of a customer-such as a manufacturer, reseller, or original equipment manufacturer-would see it. The focus is on testing bus interfaces because it is more complex than testing backplanes.<> View full abstract»

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High-quality technical articles from designers, systems integrators, and users discussing the design, performance, or application of microcomputer and microprocessor systems.

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Erik R. Altman
School of Electrical and Computer Engineering
IBM T.J. Watson Research Center