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IEEE Transactions on Computers

Issue 11 • Nov. 1974

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Displaying Results 1 - 22 of 22
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1974, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1974, Page(s): c2
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  • Interconnections for Parallel Memories to Unscramble p-Ordered Vectors

    Publication Year: 1974, Page(s):1105 - 1115
    Cited by:  Papers (19)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3400 KB)

    Several methods have been considered for storing arrays in a parallel memory system so that various useful partitions of an array can be fetched from the memory with a single access. Some of these methods fetch vectors in an order scrambled from that required for a computation. This paper considers the problem of unscrambling such vectors when the vectors belong to a class called p-ordered vectors... View full abstract»

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  • A Problem in Multiprogrammed Storage Allocation

    Publication Year: 1974, Page(s):1116 - 1122
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2656 KB)

    A simple mathematical model of (time-varying), program demand for main memory is developed. The model is based on the use of the immigration-death process, and is particularly suited to modeling the total demand of several programs. The goal is to study the behavior of the system under various schemes of dynamically allocating main memory among the programs. In particular, given some sort of worki... View full abstract»

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  • Magnitude of Cross-Coupling Noise in Digital Multiwire Transmission Lines

    Publication Year: 1974, Page(s):1122 - 1132
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4288 KB)

    Characteristics of a multiwire transmission line with inhomogeneous medium, as used for wiring in digital equipment, are investigated with respect to the cross-coupling noise, or cral. Formulas of crosstalk magnitudes are derived. Then they are simplifled for two specific kinds of transmission lines, i. e., a kind of strip lines and a line with equalized coupling. They are ready for straight-forwa... View full abstract»

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  • Comparison of Parallel and Deductive Fault Simulation Methods

    Publication Year: 1974, Page(s):1132 - 1138
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3920 KB)

    A comparison of the central processing unit (CPU) time and storage requirements for the parallel and deductive fault simulation techniques is presented. Versions of a parallel and deductive simulator were implemented and the comparison performed on an IBM System/360 Model 67 by simulating representative circuits including shift registers, sequencers, counters, two memory units, and a processor. Th... View full abstract»

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  • On the Design of Logic Networks with Redundancy and Testability Considerations

    Publication Year: 1974, Page(s):1139 - 1149
    Cited by:  Papers (38)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3304 KB)

    The presence of redundancy in combinational networks increases the cardinality of the test set to detect all stuck-at-faults. A solution to this problem is to identify and remove all redundancies in the networks before deriving test sets. It is shown in this paper that the identification of redundancy in arbitrary combinational networks is an extremely tedious problem. View full abstract»

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  • Design Technique of Fail-Safe Sequential Circuits Using Flip-Flops For Internal Memory

    Publication Year: 1974, Page(s):1149 - 1154
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3600 KB)

    A method for the realization of fail-safe sequential circuits is presented where flip-flops are employed for representing the internal states. First, such a design technique where the circuit will be trapped in an erroneous state into which it is transferred by a fault is shown. Further, the condition for assuring that the circuit will be dropped into the particular (predetermined) final state whe... View full abstract»

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  • Minimal Memory Inverses of Linear Sequential Circuits

    Publication Year: 1974, Page(s):1155 - 1163
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2568 KB)

    A necessary and sufficient condition for a linear sequential circuit to possess a feedforward inverse is given. This condition for existence of a feedforward inverse is given in terms of the Markov parameters rather than the minors of the transfer function matrix of the linear sequential circuit as has been the case in previous studies on this problem. An upper bound on the required memory of a fe... View full abstract»

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  • The Logic Machine: A Modular Computer Design System

    Publication Year: 1974, Page(s):1164 - 1169
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2368 KB)

    A digital electronic hardware design and construction system is described. Basic to the system is a microprogrammed control processor which is used unmodified in all devices constructed using this technique. This processor has no data manipulation capabilities; all arithmetic, logic, and I/O capabilities are supplied by logically complete hardware modules called functional units. The processor sup... View full abstract»

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  • An Almost-Optimal Algorithm for the Assembly Line Scheduling Problem

    Publication Year: 1974, Page(s):1169 - 1174
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3504 KB)

    This paper considers a solution to the multiprocessor scheduling problem for the case where the ordering relation between tasks can be represented as a tree. Assume that we have n identical processors, and a number of tasks to perform. Each task Tirequires an amount of time μito complete, 0 < μi≤ k, so that k is an upper bound on task time. Tasks... View full abstract»

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  • A Means for Achieving a High Degree of Compaction on Scan-Digitized Printed Text

    Publication Year: 1974, Page(s):1174 - 1179
    Cited by:  Papers (43)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3600 KB)

    A method of video compaction based on transmitting only the first instance of each class of digitized patterns is shown to yield a compaction ratio of 16: 1 on a short passage of text from the IEEE SPECTRUM. Refinements to extend the bandwidth reduction to 40: 1 by relatively simple means are proposed but not demonstrated. View full abstract»

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  • Finding Prototypes For Nearest Neighbor Classifiers

    Publication Year: 1974, Page(s):1179 - 1184
    Cited by:  Papers (168)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3328 KB)

    A nearest neighbor classifier is one which assigns a pattern to the class of the nearest prototype. An algorithm is given to find prototypes for a nearest neighbor classifier. The idea is to start with every sample in a training set as a prototype, and then successively merge any two nearest prototypes of the same class so long as the recognition rate is not downgraded. The algorithm is very effec... View full abstract»

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  • Reconfiguration for Repair in a Class of Universal Logic Modules

    Publication Year: 1974, Page(s):1185 - 1194
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2792 KB)

    A class of universal finite-state machine structures employing arrays of identical modules is shown to be capable of dynamic repair by the process of reconfiguration. Coverage on the order of 98 percent of all stuck-at faults is demonstrated with no redesign of the array being necessary. After specifying a formal model for the array structure, a complete theory is developed capable of determining ... View full abstract»

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  • Application of Multithreshold Elements in the Realization of Many-Valued Logic Networks

    Publication Year: 1974, Page(s):1194 - 1198
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2080 KB)

    Multithreshold many-valued switching primitives are introduced. Their usefulness in the construction of many-valued storage elements is demonstrated. It is shown that they can be advantageously employed in large combinational networks, such as those found in arithmetic units. View full abstract»

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  • An Example Computer Logic Graph and Its Partitions and Mappings

    Publication Year: 1974, Page(s):1198 - 1204
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1152 KB)

    The purpose of this correspondence is to provide an example computer logic graph and data concerning various partitions and mappings of this graph. This information should be of particular interest to those workers who are developing partitioning and mapping algorithms, since it provides a means to test and compare alternative methods. It should also be of use to those interested in other algorith... View full abstract»

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  • Easily Testable Two-Dimensional Cellular Logic Arrays

    Publication Year: 1974, Page(s):1204 - 1207
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (856 KB)

    An algorithm to synthesize two-dimensional AND-EOR arrays is given. The design criterion chosen is to minimize the number of columns in the two-dimensional cellular arrays. It is also shown that And-Eor arrays, synthesized using the algorithm presented, can be modified such that 2n + 5 test vectors will detect any single fault in the array realizing an n-variable function with only one observable ... View full abstract»

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  • Optimal and Near-Optimal Checking Experiments for Output Faults in Sequential Machines

    Publication Year: 1974, Page(s):1207 - 1213
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1576 KB)

    An algorithmic procedure for designing optimal and near-optimal checking sequences for output faults is presented. For the specific cases where minimum length cannot be guaranteed, the algorithm also determines an upper bound on the excess length of the resulting sequence. Several extensions of the method are discussed, such as the application of output checking sequences for diagnosing purposes. ... View full abstract»

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  • Evaluation of Walsh Power Spectrum of Nearly White Signals

    Publication Year: 1974, Page(s):1213 - 1214
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    An expression for evaluating the Walsh power spectra of random signals with very short time correlations is given. View full abstract»

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  • B74-42 Introduction to Discrete Structures

    Publication Year: 1974, Page(s):1215 - 1216
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  • IEEE Computer Society Publications

    Publication Year: 1974, Page(s): 1216-a
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  • IEEE Computer Society Membership & Publications

    Publication Year: 1974, Page(s): 1216
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org