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Computers, IEEE Transactions on

Issue 10 • Date Oct. 1974

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Displaying Results 1 - 17 of 17
  • IEEE Transactions on Computers - Table of contents

    Page(s): c1
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  • IEEE Computer Society

    Page(s): c2
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  • Fourier Transform Computers Using CORDIC Iterations

    Page(s): 993 - 1001
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    The CORDIC iteration is applied to several Fourier transform algorithms. The number of operations is found as a function of transform method and radix representation. Using these representations, several hardware configurations are examined for cost, speed, and complexity tradeoffs. A new, especially attractive FFT computer architecture is presented as an example of the utility of this technique. Compensated and modified CORDIC algorithms are also developed. View full abstract»

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  • Weight-Preserved Single-Error-Correcting Scheme for Binary Adders

    Page(s): 1002 - 1007
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    A new single-error-correcting scheme for binary adders is devised in this paper. A new weight function [called the Arithmetic Series Weight Function (ASWF)] of binary integers is defined. By using this weight function, a simple weight-preserved relation among the operands, sums and carries of binary adders is obtained. The error-correcting scheme is based on this relation. The redundancy of this scheme is comparable to that of the other error-control techniques in binary computer arithmetic. Moreover, the error-correcting procedure is simple and can be carried out by solving a simple algebraic equation involving only additive operations. View full abstract»

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  • Unate Cascade Realization of Synchronous Sequential Machines

    Page(s): 1008 - 1019
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    In this paper the problems associated with the minimal realization of synchronous sequential machines by unate cellular cascades have been studied. Given the sequential machine in the form of a flow table, a systematic procedure is followed to generate all the selectable sets. Compatible sets consisting of these selectable sets are next determined and the different secondary variables are assigned. The nested functional forms of the next-state expressions for these variables are finally established. The proposed method is very systematic and perfectly suited for machine processing. View full abstract»

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  • Asynchronous Control Arrays

    Page(s): 1020 - 1029
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    This paper introduces a class of programmable cellular arrays, called control arrays, and presents a technique for programming these arrays to realize asynchronous control systems. Control arrays are two-dimensional uniform networks composed of a collection of identical cells that can be independently programmed to one of two internal states. A control system is a device that controls one or more operations by means of initiation and termination signals that are transmitted through bidirectional control links. A control system model is developed by augmenting the marked graph model in order to represent constraints on the generation of these control signals. Finally, an array synthesis procedure for realizing control systems with control arrays is presented. View full abstract»

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  • Redundancy Testing in Combinational Networks

    Page(s): 1029 - 1047
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    A simple, necessary and sufficient test is developed for testing whether a single connection in a tree-type NAND network is redundant. A procedure is presented for testing every connection in the network. The computational complexity of the procedure is mi2 where m = the number of gates and i = the average number of inputs per gate in the network. View full abstract»

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  • Direct Transition Memory and its Application in Computer Design

    Page(s): 1048 - 1061
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    This paper investigates a potential application of microprogrammable memories to the problem of sequential network synthesis and computer design. It is shown that by allowing a controllable amount of memory redundance, a microprogrammed emulation of a state table can be organized such that decision branches in the microprogram are achieved in an immediate multiport manner, without the need of additional branch steps in the microprogram, thus increasing operational speed. A design technique is developed which, for a given state table, allows a minimum number of memory address variables to be used while minimizing the dependence of the variables on both the input and current state information. This technique has immediate practical application in the design of sequential networks, and is shown to be feasible in the controller design of a general purpost computer. View full abstract»

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  • Optimal Routing in a Packet-Switched Computer Network

    Page(s): 1062 - 1069
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    The problem of finding optimal routes in a packet-switched computer network can be formulated as a nonlinear multicommodity flow problem. View full abstract»

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  • Procedures for Eliminating Static and Dynamic Hazards in Test Generation

    Page(s): 1069 - 1078
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    One problem associated with test generation algorithms for sequential circuits is that they often produce tests which, when applied to the circuit under test, create static and/or dynamic hazards which may invalidate the test. Usually, for static hazards, but not dynamic hazards, these situations can be predicted using a logic simulator. In this paper we present procedures which can be added to path sensitization test generation algorithms so that the resulting procedure will not produce tests which will be invalidated due to hazards. Incidental to this work is a new simulation technique for handling both static and dynamic hazards. The principal concepts behind this work deal with detecting when hazards are created in a circuit; propagating hazard status information related to a signal line through a circuit; detecting those conditions at flip-flop inputs which necessitate hazard free conditions; and finally, selecting test inputs so that all hazard free conditions are satisfied. View full abstract»

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  • The Effects of Races, Delays, and Delay Faults on Test Generation

    Page(s): 1078 - 1092
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    Test sequences constructed by most test generation procedures often create time dependent results when applied to a circuit. These dependencies often invalidate the test. The main cause for this situation is that the test generation procedures and circuit models employed do not take into account many aspects of delay associated with a circuit. In this paper we present modeling techniques to be used by conventional test generation procedures to alleviate some of these problems. These models include the cases of equal, unequal and ambiguous delay values. Both inertial and transport delays are considered. Both static and dynamic output behavior is studied, though we restrict inputs to fundamental mode operation. Finally, a new type of fault, caUed a delay fault, is introduced, and a model developed so that a test to detect this class of fault can be generated via conventional test generation techniques. In summary, this paper attempts to outline procedures and identify problem areas so that test generation is more of a science rather than a hit and miss process, and so that the correctness of results need not always be verified via simulation or physical fault injection. View full abstract»

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  • A Method for Solving Polynomial Equations by Continued Fractions

    Page(s): 1093 - 1097
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    A method for the approximation of all the real roots of an n-order polynomial equation is developed. It is assumed that intervals containing the solutions are known. Bilinear transformations are used to approximate the solution. Convergence is achieved. View full abstract»

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  • On the Solution of Boolean and Pseudo-Boolean Relations

    Page(s): 1098 - 1100
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    This correspondence deals with collections of n binary relations between Boolean and/or pseudo-Boolean functions which are combined by an n-ary relation. A new algorithm is described for solving these relations. View full abstract»

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  • Note on Self-Checking Checkers

    Page(s): 1100 - 1102
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    Totally self-checking checkers for k-out-of-(2k + 1), (k + 1)-out-of-(2k + 1), and k-out-of-2k codes are given. The new checkers for the k-out-of-2k codes require only 2k tests to detect all stuck-at faults. View full abstract»

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  • B74-41 The Metaphorical Brain, an Introduction to Cybernetics as Artificial Intelligence and Brain Theory

    Page(s): 1103 - 1104
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  • IEEE Computer Society Publications

    Page(s): 1104-a
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  • IEEE Computer Society Membership & Publications

    Page(s): 1104
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Albert Y. Zomaya
School of Information Technologies
Building J12
The University of Sydney
Sydney, NSW 2006, Australia
http://www.cs.usyd.edu.au/~zomaya
albert.zomaya@sydney.edu.au