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Computers, IEEE Transactions on

Issue 1 • Date Jan. 1974

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Displaying Results 1 - 25 of 29
  • IEEE Transactions on Computers - Table of contents

    Page(s): c1
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    Freely Available from IEEE
  • IEEE Computer Society

    Page(s): c2
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    Freely Available from IEEE
  • Fast Computational Algorithms for Bit Reversal

    Page(s): 1 - 9
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    Radix—2 fast Fourier transform programs of the Gentleman-Sande type leave the transformed array in a scrambled order of frequencies. Unscrambling is accomplished by moving each element from its present location into a new location obtained by bit reversal. Bit reversal can be interpreted as an exchange of groups of bits symmetric with respect to a pivot. Two formulas are developed for simultaneous and sequential exchanging in place, with negligible auxiliary storage. Programs for one-step and sequential unscrambling were implemented. Binary unscrambling is useful to unscramble large arrays in peripheral storage. The one-step unscrambling program presented is more efficient than other programs available in the literature. View full abstract»

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  • Floating-Point Arithmetic Algorithms in the Symmetric Residue Number System

    Page(s): 9 - 20
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    The residue number system is an integer number system and is inconvenient to represent numbers with fractional parts. In the symmetric residue system, a new representation of floating-point numbers and arithmetic algorithms for its addition, subtraction, multiplication, and division are proposed. A floating-point number is expressed as an integer multiplied by a product of the moduli. The proposed system assumes existence of necessary conversion procedures before and after the computation. View full abstract»

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  • Towards a Theory of Universal Speed-Independent Modules

    Page(s): 21 - 33
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    Of concern here are asynchronous modules, i.e., those whose activity is regulated by initiation and completion signals with no clocks being present. First a number of operating conditions are described that are deemed essential or useful in a system of asynchronous modules, while retaining an air of independence of particular hardware implementations as much as possible. Second, some results are presented concerning sets of modules that are universal with respect to these conditions. That is, from these sets any arbitrarily complex module may be constructed as a network. It is stipulated that such constructions be speed independent, i.e., independent of the delay time involved in any constituent modules. Furthermore it is required that the constructions be delay insensitive in the sense that an arbitrary number of delay elements may be inserted into or removed from connecting lines without effecting the external behavior of the network. View full abstract»

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  • On Two-Level Exclusive-or Majority Networks

    Page(s): 34 - 41
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    It is shown that not all Boolean functions can be realized by a two-level EXCLUSIVE-OR majority network. However, if repeats at the first level are allowed, then it is shown that such a network is universal. A minimal weight vector with respect to this latter network is defined. By using the restricted-affine-group (RAG) equivalence of Boolean functions, it is shown that if two functions are in the same RAG class, then they are realized by the same minimal weight vector to within permutations and/or sign changes. View full abstract»

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  • Design of Two-Level Fault-Tolerant Networks

    Page(s): 41 - 48
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    Some new techniques for the synthesis of fault-tolerant two-level combinational networks are presented. Two classes of faults are defined, 1) critical faults and 2) subcritical faults. Critical fauls are the class of faults that cannot be tolerated by any two-level networks. Necessary conditions for synthesis of networks tolerating subcritical faults are developed. As a result it is established that the conditions required for tolerating faults in the logic elements and those required for tolerating faults in the primary inputs are significantly different. Several design techniques are presented and it is shown that if we restrict our class of faults, then certain normally assumed conditions on redundancy can be relaxed. A class of hazards is defined. It is shown that the synthesis of certain hazard-free realizations is equivalent to the fault-tolerant realization, and also an upper bound on the redundancy of the fault-tolerant realization is derived. View full abstract»

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  • Multiple-Fault Detection and Location in Fan-Out Free Combinational Circuits

    Page(s): 48 - 55
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    Two algorithms are presented for the detection and location of single or multiple stuck faults in a fan-out free combinational circuit. The algorithms are based on a canonic representation of the indistinguishability classes of faults. The number of tests required in these algorithms are shown to be a linear function of the number of gates in the circuit. View full abstract»

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  • On Modifying Logic Networks to Improve Their Diagnosability

    Page(s): 56 - 62
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    This paper considers the use of control logic to reduce the number of tests required by a logic network and to simplify test generation. The properties of EXCLUSIVE-OR (EOR) circuits as control elements are examined. Systematic procedures are presented for modifying any combinational or sequential network so that the resulting network requires only five tests. These tests can easily be generated using a set of predefined test patterns of length five. The design of diagnosable networks using a limited amount of control logic is also discussed. View full abstract»

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  • Optimal One-Bit Full Adders With Different Types of Gates

    Page(s): 63 - 70
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    Optimal networks with thirty different types of restrictions are listed for the one-bit fuli adder. Optimality is derined as the minimization of the number of gates under different restrictions. View full abstract»

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  • On a New Class of Bounds on Bayes Risk in Multihypothesis Pattern Recognition

    Page(s): 70 - 80
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    An important measure concerning the use of statistical decision schemes is the error probability associated with the decision rule. Several methods giving bounds on the error probability are presently available, but, most often, the bounds are loose. Those methods generally make use of so-cailed distances between statistical distributions. In this paper a new distance is proposed which permits tighter bounds to be set on the error probability of the Bayesian decision rule and which is shown to be closely related to several certainty or separability measures. Among these are the nearest neighbor error rate and the average conditional quadratic entropy of Vajda. Moreover, our distance bears much resemblance to the information theoretic concept of equivocation. This relationship is discussed. Comparison is made between the bounds on the Bayes risk obtained with the Bhattacharyya coefficient, the equivocation, and the new measure which we have named the Bayesian distance. View full abstract»

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  • State Minimization of Incompletely Specified Sequential Machines

    Page(s): 80 - 84
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    A simple procedure for the state minimization of an incompletely specified sequential machine whose number of internal states is not very large is presented. It introduces the concept of a compatibility graph from which the set of maximal compatibles of the machine can be very conveniently derived. Primary and secondary implication trees associated with each maximal compatible are then constructed. The minimal state machine covering the incompletely specified machine is then obtained from these implication trees. View full abstract»

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  • A State Assignment Technique for Sequential Machines Using J-K Flip-Flops

    Page(s): 85 - 86
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    Several techniques for choosing state assignments which tend to minimize the combinational input and output circuitry of sequential machines have been developed. One of these techniques is a heuristic scoring approach which was originally developed assuming delays as memory elements [1]. View full abstract»

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  • Characterization of Connection Assignment of Diagnosable Systems

    Page(s): 86 - 88
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    Preparata, Metze, and Chien [1] gave necessary conditions for identification of all faulty units in a system S capable of automatic fault diagnosis. We show that these conditions are sufficient if in S no two units test each other. Necessary and sufficient conditions are also obtained for the general case when no such restriction is placed on S. View full abstract»

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  • A New Algorithm for Computing Correlations

    Page(s): 88 - 90
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    In this correspondence we present a new algorithm for computing the correlation [mi][/mi]. For applications where the "cost" of a multiplication is greater than that of an addition, the new algorithm is always more computationally efficient than direct evaluation of the correlation, and it is generally more efficient than FFT methods for processing 128 or fewer data points, or for calculating only the first L values of Rk, for L < 10 log2 2N. View full abstract»

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  • Discrete Cosine Transform

    Page(s): 90 - 93
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    A discrete cosine transform (DCT) is defined and an algorithm to compute it using the fast Fourier transform is developed. It is shown that the discrete cosine transform can be used in the area of digital processing for the purposes of pattern recognition and Wiener filtering. Its performance is compared with that of a class of orthogonal transforms and is found to compare closely to that of the Karhunen-Loève transform, which is known to be optimal. The performances of the Karhunen-Loève and discrete cosine transforms are also found to compare closely with respect to the rate-distortion criterion. View full abstract»

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  • Minimization of Linear Sequential Machines

    Page(s): 93 - 95
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    An algorithm is presented to minimize linear sequential machines to reduced form. View full abstract»

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  • Sequential Algorithm for the Determination of Maximum Compatibles

    Page(s): 95 - 98
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    This correspondence describes an algorithm which finds the maximum compatibles (maximal complete subgraphs of a symmetric graph) sequentially and in lexicographic order. The algorithm is intended for use in digital computers, where it requires only a small program and very little memory space. View full abstract»

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  • Easily Testable Cellular Realizations for the (Exactly P)-out-of n and (p or More)-out-of n Logic Functions

    Page(s): 98 - 100
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    Networks to realize all n-variable symmetric threshold functions and elementary symmetric functions are given. It is also shown that only 2n test inputs are necessary and sufficient to test any number of faults in these networks. View full abstract»

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  • A Computational Algorithm for Solving a System of Coupled Algebraic Matrix Riccati Equations

    Page(s): 100 - 102
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    A computational algorithm for solving a system of coupled matrix algebraic equations is presented in this paper. Such equations arise in optimal control problems of linear systems with jump parameters. View full abstract»

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  • Quantization Complexity and Independent Measurements

    Page(s): 102 - 106
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    It is known that, in general, the number of measurements in a pattern classification problem cannot be increased arbitrarily, when the class-conditional densities are not completely known and only a finite number of learning samples are available. Above a certain number of measurements, the performance starts deteriorating instead of improving steadily. It was earlier shown by one of the authors that an exception to this "curse of finite sample size" is constituted by the case of binary independent measurements if a Bayesian approach is taken and uniform a priori on the unknown parameters are assumed. In this paper, the following generalizations are considered: arbitrary quantization and the use of maximum likelihood estimates. Further, the existence of an optimal quantization complexity is demonstrated, and its relationship to both the dimensionality of the measurement vector and the sample size are discussed. It is shown that the optimum number of quantization levels decreases with increasing dimensionality for a fixed sample size, and increases with the sample size for fixed dimensionality. View full abstract»

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  • A Novel Implementation Method for Addition and Subtraction in Residue Number Systems

    Page(s): 106 - 109
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    This correspondence describes an implementation scheme for the operations of addition and subtraction in the residue number systems. The method is based on the property that the set of residues modulo m form a finite group under addition and subtraction (modulo m). The proposed adder/subtractor structure is very systematic and, hence, suitable for MSI/LSI realization. View full abstract»

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  • B74-1 Complexity of Computer Computations

    Page(s): 109 - 110
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    Freely Available from IEEE
  • B74-2 Man and the Computer

    Page(s): 110
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    Freely Available from IEEE
  • B74-3 Design Automation of Digital Systems–Volume 1, Thoery and Techniques

    Page(s): 110 - 111
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    Freely Available from IEEE

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Albert Y. Zomaya
School of Information Technologies
Building J12
The University of Sydney
Sydney, NSW 2006, Australia
http://www.cs.usyd.edu.au/~zomaya
albert.zomaya@sydney.edu.au