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IEEE Transactions on Computers

Issue 3 • Date March 1973

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Displaying Results 1 - 19 of 19
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1973, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1973, Page(s): c2
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  • Fault-Tolerant Computing: An Introduction and a Viewpoint

    Publication Year: 1973, Page(s):225 - 229
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2392 KB)

    AFTER approximately 20 years of obscurity, the field of fault-tolerant computing was revived by the formation of the IEEE Technical Committee on Fault-Tolerant Computing, by a series of articles in COMPUTER for January/ February 1971, by the 1971 International Symposium on Fault-Tolerant Computing in Pasadena, Calif., and by an IEEE TRANSACTIONS ON COMPUTERS Special Issue on Fault-Tolerant Computi... View full abstract»

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  • Use of SPOOF's in the Analysis of Faulty Logic Networks

    Publication Year: 1973, Page(s):229 - 234
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3664 KB)

    In general, one cannot predict the effects of possible failures on the functional characteristics of a logic network without knowlegde of the structure of that network. View full abstract»

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  • Multiple Fault Detection in Combinational Circuits: Algorithms and Computational Results

    Publication Year: 1973, Page(s):235 - 240
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2776 KB)

    A new approach is developed for finding multiple fault detection tests under quite arbitrary fault models. Computational results are reported and discussed. View full abstract»

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  • Testing for Intermittent Faults in Digital Circuits

    Publication Year: 1973, Page(s):241 - 246
    Cited by:  Papers (48)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2312 KB)

    In this paper we present a few fundamental results related to the problems of characterization and detection of intermittent faults in digital circuits, which, up to now, have been almost totally ignored. This problem is important since in many technologies intermittency is a predominant mode of failure. View full abstract»

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  • Figure of Merit for Fault-Tolerant Space Computers

    Publication Year: 1973, Page(s):246 - 251
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3600 KB)

    To aid the computer designer in addressing the proper reliability goals, an economic model is proposed in which any increase in cost for reliability is evaluated against the expected decrease in cost of failure. These criteria are applied in an example to optimize the memory configuration of a computer that has a five-year lifetime requirement in space. An internal figure of merit is developed tha... View full abstract»

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  • The Concept of Coverage and Its Effect on the Reliability Model of a Repairable System

    Publication Year: 1973, Page(s):251 - 254
    Cited by:  Papers (115)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3176 KB)

    Duplication is a technique frequently employed to achieve high reliability for a repairable system. Although the philosophy of duplication is that it takes two faults to place a system out of service, there are generally some critical single faults that cause a system failure. This paper considers the effect of such a set of faults on a repairable system's reliability. It is shown that even a smal... View full abstract»

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  • Design of a Self-Checking Microprogram Control

    Publication Year: 1973, Page(s):255 - 262
    Cited by:  Papers (62)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2832 KB)

    In designing a self-checking processor, it is essential to recognize the types of failures that are most probable. Matching the checking techniques with the type of faults that are expected to occur should yield the best result with the least amount of hardware. The microprogram control will consist of integrated circuits: large-scale integration (LSI) for the memory and small-scale integration (S... View full abstract»

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  • Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes

    Publication Year: 1973, Page(s):263 - 269
    Cited by:  Papers (269)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2616 KB)

    The design of totally self-checking check circuits for m-out-of-n codes is described. Totally self-checking m-out-of-n checkers provide an error indication whenever the input is not an m-out-of-n code or whenever a fault occurs within the checker itself. Since the checker checks itself, there is no need for additional maintenance access or periodic exercise of the checker to verify its ability to ... View full abstract»

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  • Modeling of a Bubble-Memory Organization with Self-Checking Translators to Achieve High Reliability

    Publication Year: 1973, Page(s):269 - 275
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4184 KB)

    This paper reports a study on the design and modeling of a highly reliable bubble-memory system. This system has the capability of correcting a single 16-adjacent bit-group error resulting from failures in a single basic storage module (BSM), and detecting with a probability greater than 0.99 any double errors resulting from failures in BSM's. The encoding/decoding network (memory translator) is d... View full abstract»

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  • Switch Complexity in Systems with Hybrid Redundancy

    Publication Year: 1973, Page(s):276 - 282
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2800 KB)

    The combination of N-modular redundancy (NMR) and standby sparing has resulted in a promising redundancy technique for protecting those portions of a fault-tolerant system whose continuous real-time operation is essential. This technique, known as hybrid redundancy, uses N + Sp identical modules. N of these are connected to a majority voter to form an NMR core. The remaining Sp are used as standby... View full abstract»

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  • Lookaside Techniques for Minimum Circuit Memory Translators

    Publication Year: 1973, Page(s):283 - 289
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2488 KB)

    This paper demonstrates two improvements in coding techniques that could be used for memory word coding. First, within the fixed structure of a Hamming single-error-correcting, double-error-detecting (SEC/DED) code, an improvement can be obtained in circuit cost and operational speed over more conventional code implementations. Second, the mechanics of error correction in a fault-tolerant computer... View full abstract»

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  • An Iterative Cell Switch Design for Hybrid Redundancy

    Publication Year: 1973, Page(s):290 - 297
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1424 KB)

    A marriage of N-modular redundancy (NMR) and standby sparing has resulted in a promising redundancy technique for protecting those portions of a fault-tolerant system whose continuous real-time operation is essential. This technique, known as hybrid redundancy, consists of N identical modules connected to a majority voter to form an NMR core. Disagreement detectors instruct a switch to replace any... View full abstract»

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  • Shared Logic Realizations of Dynamically Self-Checked and Fault-Tolerant Logic

    Publication Year: 1973, Page(s):298 - 306
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2568 KB)

    Dynamically self-checked or fault-tolerant realizations of switching functions and sequential machines are proposed under a fault model that permits arbitrary logic faults in a single-logic module, where the modules are explicitly defined. These realizations permit considerable logic sharing, organized around an (n, m, r)-basis for decomposing switching functions. The logic sharing permits more ec... View full abstract»

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  • Error Correcting Properties of Redundant Residue Number Systems

    Publication Year: 1973, Page(s):307 - 315
    Cited by:  Papers (71)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2808 KB)

    The error correcting properties of the redundant residue number systems (RNS) are investigated through a more natural a approach than was previously known. The necessary and sufficient condition for the correction of a given error affecting a single residue digit of any legitimate number in an RRNS is determined. The minimal redundancy allowing the correction of the whole class of the single resid... View full abstract»

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  • IEEE Computer Society Membership & Publications

    Publication Year: 1973, Page(s): 315
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  • Information for authors

    Publication Year: 1973, Page(s): 315
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  • Blank Page

    Publication Year: 1973, Page(s): 315
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org