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IEEE Transactions on Computers

Issue 11 • Date Nov. 1973

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Displaying Results 1 - 17 of 17
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1973, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1973, Page(s): c2
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  • Editor's Notice

    Publication Year: 1973, Page(s): 965
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  • Analog Solutions of Nonlinear Boundary-Value Problems by the Continuation Method

    Publication Year: 1973, Page(s):966 - 970
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1880 KB)

    The analog solution of nonlinear two-point boundary-value problems by the noniterative continuation method is described. It is shown that a two-point boundary-value problem can be reformulated as a rather complicated initial-value problem. The solution of this latter problem is demonstrated for a simple example, on a modern analog computer with fast repetitive mode. A special emphasis is put on th... View full abstract»

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  • Numerical Technique for the Convolution of Piecewise Polynomial Functions

    Publication Year: 1973, Page(s):970 - 975
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2984 KB)

    This paper describes a general systematic procedure for the convolution of functions that are piecewise polynomial. The procedure can be implemented by hand using a simple table format or programmed for execution on a digital computer. An algebraic convolution law is dermed to replace integration; this provides an efficient digital computation algorithm. Thus, convolution operations of any complex... View full abstract»

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  • A Research-Oriented Dynamic Microprocessor

    Publication Year: 1973, Page(s):976 - 985
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2880 KB)

    A horizontally structured microprogrammable processor (AMP) designed as a tool for microcontrol, language, and processor design research, is described. The machine employs a minimally encoded microcontrol word, a very general multiple bus structure, highspeed local storage, several arithmetic/logic units, and completely asynchronous memory referencing. These features combine to yield substantial l... View full abstract»

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  • Compilation Techniques for Recognition of Parallel Processable Tasks in Arithmetic Expressions

    Publication Year: 1973, Page(s):986 - 998
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3360 KB)

    With the developments of parallel computer systems, the techniques for the recognition and representation of parallel task streams in a job (program) have become important to enhance the system performance. View full abstract»

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  • Multiple Microprocessors with Common Main and Control Memories

    Publication Year: 1973, Page(s):999 - 1007
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2912 KB)

    This paper investigates some of the problems that arise when several microprocessors share a common control memory and a common main memory. The performance with respect to both control and main memory accessing conflicts is measured for several system configurations by means of a simulation program. The program tests a set of Digital Scientific Meta 4's operating in IBM 1130 emulation mode. View full abstract»

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  • Fault Folding for Irredundant and Redundant Combinational Circuits

    Publication Year: 1973, Page(s):1008 - 1015
    Cited by:  Papers (48)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2056 KB)

    Fault folding is the process of applying test equivalent or test implied relations from a primary output towards the connected primary inputs in order to find a reduced set of faults that cover the set of faults on the intervening network. View full abstract»

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  • Complete Test Sets for Logic Functions

    Publication Year: 1973, Page(s):1016 - 1020
    Cited by:  Papers (56)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (848 KB)

    The problem of designing fault detecting test sets from the functional description rather than the structural description of the networks realizing the logic function is studied. The concept of an expanded truth table for logic functions is introduced. It is proved that the set of minimal true vertices and maximal false vertices of the expanded truth table constitutes a test set to detect any numb... View full abstract»

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  • Parallel Counters

    Publication Year: 1973, Page(s):1021 - 1024
    Cited by:  Papers (90)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    Multiple-input circuits that count the number of their inputs that are in a given state (normally logic ONE) are called parallel counters. In this paper three separate types of counters are described, analyzed, and compared. The first counter consists of a network of full adders. The second counter uses a combination of full adders and fast adders (that may be realized with READ-ONLY memories), wh... View full abstract»

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  • Clustering Using a Similarity Measure Based on Shared Near Neighbors

    Publication Year: 1973, Page(s):1025 - 1034
    Cited by:  Papers (285)  |  Patents (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4808 KB)

    A nonparametric clustering technique incorporating the concept of similarity based on the sharing of near neighbors is presented. In addition to being an essentially paraliel approach, the computational elegance of the method is such that the scheme is applicable to a wide class of practical problems involving large sample size and high dimensionality. No attempt is made to show how a priori probl... View full abstract»

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  • The Polish Assembler

    Publication Year: 1973, Page(s):1035 - 1040
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2072 KB)

    A load-and-go resident assembler using approximately 2500 words in a 16-b computer is described. It was designed for writing system programs, and assembles sufficiently fast so that there is little incentive to keep programs in object form. The assembler is table driven and can be adapted to various computers relatively easily. View full abstract»

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  • Hazard Correction in Asynchronous Sequential Circuits Using Inertial Delay Elements

    Publication Year: 1973, Page(s):1041 - 1042
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    This correspondence is concerned with the use of inertial delay elements for the correction of influences of aith-order hazards and races among internal signals on the activity of asynchronous sequential circuits. View full abstract»

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  • A Note on a Modified Ternary Simulator Capable of Initializing All Fault Machine Memory Elements

    Publication Year: 1973, Page(s):1042 - 1044
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    Generation of test patterns and diagnostics for complex digital modules often involves a ternary (0, 1, u) simulation program. A non-Boolean technique, presented herein, initializes u (unknown) values in such a way that diagnostic resolution and accuracy is enhanced. A pure ternary simulator lacks this initialization capability. View full abstract»

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  • Information for authors

    Publication Year: 1973, Page(s): 1044
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  • Peripherals

    Publication Year: 1973, Page(s): 1044-b
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org