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Computers, IEEE Transactions on

Issue 10 • Date Oct. 1972

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Displaying Results 1 - 21 of 21
  • IEEE Transactions on Computers - Table of contents

    Page(s): c1 - 1152
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  • IEEE Computer Society

    Page(s): c2
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  • An Adaptive Replacement Algorithm for Paged-Memory Computer Systems

    Page(s): 1053 - 1061
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    A general class of adaptive replacement schemes for use in paged memories is developed. One such algorithm, called SIM, is simulated using a probability model that generates memory traces, and the results of the simulation of this adaptive scheme are compared with those obtained using the best nonlookahead algorithms. A technique for implementing this type of adaptive replacement algorithm with state of the art digital hardware is also presented. View full abstract»

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  • The Design or Multipoint Linkages in a Teleprocessing Tree Network

    Page(s): 1062 - 1066
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    The problem of designing a minimum cost network with multipoint linkages which connects several remote terminals to a data processing center is studied. The important aspects of a teleprocessing network are queue behavior at the terminals and the cost and reliability of the entire system. In this paper it is assumed that the rate and manner in which information is requested at the terminals is known and that acceptable line loadings are given. An algorithm that determines (in principle) the optimum minimum cost network subject to reliability constraints is developed. A heuristic based on Vogel's approximation method (VAM) and two other heuristics presented by Martin and Esau-Williams were compared with each other and with the optimal algorithm. The Esau-Williams heuristic seems to be the one that gives the best solution and Martin's requires the least processing time. It is shown experimentally that Martin's and Esau-Williams heuristics are, in fact, near-optimal heurstics in the sense that the solutions provided by these heuristics are generally very near the optimal solution. In this paper we make the assumption that all lines of the network have the same capacity. View full abstract»

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  • Multidimensional Linear Iterative Circuits—General Properties

    Page(s): 1067 - 1073
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    This paper fornulates a state-space model for linear iterative circuits having more than one spatial dimension. A new type of matrix operation is introduced that allows treatment of such models in a relatively straightforward manner. Finally, a form for the general response is developed in terms of this new matrix operation. View full abstract»

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  • A Class of Autonomous One-Dimensional Iterative Arrays of Linear Machines

    Page(s): 1073 - 1086
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    An analysis of the state structure and of the autonomous behavior of iterative systems belonging to the class of one-dimensional unidirectional single-output autonomous iterative arrays with one intercell lead and the cell structure of a linear sequential machine (LSM) is presented. An algorithm is developed for computing the state structure of any such iterative system with the cell structure of a minimal LSM. Another algorithm computes the cycle structure of the output sequences generated by any such iterative system, with the cell structure of an arbitrary single-input single-output LSM. View full abstract»

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  • Minimum Two-Level Threslold Gate Realizations

    Page(s): 1086 - 1098
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    This paper deals with the synthesis of two-level networks of threshold gate logic elements for realization of nonlinearly separable switching functions. The realization obtained contains the minimum number of threshold logic elements possible for a two-level realization. An algorithm based on the tree procedure of Coates and Lewis is developed which can be used to obtain the desired network realization for a given switching function. The function may be incompletely specified. View full abstract»

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  • The Synthesis of Minimal Hazardless TANT Networks

    Page(s): 1099 - 1108
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    This paper presents a new algorithm Amfor the synthesis of minimum gate costs TANT networks. This algorithm, which differs in the setting up of the CC table from the known Gimpel's algorithm [1], has some very advantageous features, both in its hand solution and the computer realization. The final stage of this synthesis is the solution of the CC table. View full abstract»

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  • On Complete Systems and Finite Automata

    Page(s): 1109 - 1113
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    A production on T* is a rewriting rule σα→σ' for all aϵ T*, where σ, σ' are strings in T* with a' lexicographically earlier than σ. Any finite collection of productions is called a system. This note shows that any system that is consistent, complete, and has the nonprefix property uniquely represents an automaton. This formulation characterizes automata as recognition devices in terms of a set of rewriting rules, similar to the characterizatibn of automata as generating devices by grammars. View full abstract»

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  • A Versatile Multiplying Digital-to-Analog Converter

    Page(s): 1113 - 1116
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    A modified binary-weighted resistor multiplying digital-to-analog (MDAC) converter with a full scale (±12 V) analog bandwidth in excess of 500 kHz is described. Its settling time following changes in digital inputs of either polarity is less than 2 , μs. The dc resolution is 0.01 percent and the dynamic error increases from 0.01 percent at 50 kHz to 0.1 percent at 250 kHz. View full abstract»

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  • A Cellular Permuter Array

    Page(s): 1116 - 1119
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    A permuter network is used to arbitrarily change the ordering of the variables of a switching function. A new scheme for permuter arrays is discussed in this note whereby the variables are selected sequentially by a number of "selector cells" according to the required output ordering. A cellular realization of the selector cell is suggested. View full abstract»

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  • Additive Bernoulli Noise Linear Sequential Circuits

    Page(s): 1119 - 1124
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    In the search for new methods to realize stochastic automata, additive Bernoulli noise linear sequential circuits (ABNLSC) are constructed from linear sequential circuits fed with Bernoulli noise. The characteristics of the subclass of stochastic automata realizable by ABNLSC's are found. These characteristics include: commutativity with respect to input sequences; state minimality; doubly stochastic state transition matrices; and the conditions for the existence of asymptotic distribution of the state. View full abstract»

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  • Modular Networks and Nondeterministic Sequential Machines

    Page(s): 1124 - 1129
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    The synthesis of sequential machines by interconnections of copies of a fixed module is considered. A family of modules Mr,pfor positive integers r and p, is defined. Mr,p can be used to synthesize sequential machines with 2Pinput symbols. A nondeterministic sequential machine (NSM) is said to be r-bounded if it has one initial state and for no state and input are there more than r choices for the next state. It is shown that the problem of finding a network of modules Mr,prealizing a given event E is equivalent to finding an r-bounded NSM realizing the reverse of E. As a consequence, two upper bounds on the number of copies of the module Mr,pnecessary to realize an event E can be shown. 1) If E is defined by an n-state NSM, then E is defined by a network of at most cln2+plogr2copies of Mr,p. 2) If E is defined by an n-state deterministic sequential machine, then E is defined by a network of at most c2nl+vlogr2copies of Mr,p. cland C2are constants, about 4. View full abstract»

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  • An Iterative Technique for Determining the Minimal Number of Variables for a Totally Symmetric Function with Repeated Variables

    Page(s): 1129 - 1131
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    Several analytic procedures exist for transforming a partially symmetric switching function to a totally symmetric switching function by judiciously repeating certain variables. Presumably the best totally symmetric representation for a given function would be the one having the fewest variables. This note presents an iterative technique for finding the totally symmetric realization for a given function that has the absolute minimum number of variables. View full abstract»

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  • Contributors

    Page(s): 1132 - 1133
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  • B72-17 Computer Analysis of Circuits

    Page(s): 1133 - 1135
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  • B72-18 Computers and Their Uses, 2nd ed.

    Page(s): 1135
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  • B72-19 Future Developments in Telecommunications

    Page(s): 1135 - 1136
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  • B72-20 Computers in Busines–An Introduction, 2nd ed.

    Page(s): 1136
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  • Abstracts of Current Computer Literature

    Page(s): 1137 - 1152
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  • Information for authors

    Page(s): 1152
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Albert Y. Zomaya
School of Information Technologies
Building J12
The University of Sydney
Sydney, NSW 2006, Australia
http://www.cs.usyd.edu.au/~zomaya
albert.zomaya@sydney.edu.au