IEEE Transactions on Computers

Issue 1 • Jan. 1972

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Displaying Results 1 - 25 of 27
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1972, Page(s):c1 - 127
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  • IEEE Computer Society

    Publication Year: 1972, Page(s): c2
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  • Visible Surface Algorithms for Quadric Patches

    Publication Year: 1972, Page(s):1 - 4
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2048 KB)

    This paper describes two algorithms which find the visible portions of surfaces in a picture of a cluster of three-dimensional quadric patches. A quadric patch is a portion of quadric surface defined by a quadratic equation and by zero, one, or several quadratic inequalities. The picture is cut by parallel planes called scan planes. The visibility problem is solved in one scan plane at a time by m... View full abstract»

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  • Minimal Negative Gate Networks

    Publication Year: 1972, Page(s):5 - 11
    Cited by:  Papers (19)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1248 KB)

    A negative gate is a gate that can realize an arbitrary negative function (or monotone decreasing function) and a positive gate is one that can realize an arbitrary positive function (or monotone increasing function). This paper discusses methods of realizing a given logical function or a given set of logical functions using a minimum number of negative gates alone or using a minimum number of neg... View full abstract»

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  • A Transform for NAND Network Design

    Publication Year: 1972, Page(s):12 - 20
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1432 KB)

    A transform that operates on the interconnection topology of a NAND network is presented. The output connecting a designated gate to the network is deleted and is connected instead to a number of other gates in the network. The entire transform may be specified by designating a "transformed gate" and a "modified gate." The new connections are made and the resulting network is then simplified logic... View full abstract»

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  • A New Approach to the Fault Location of Combinational Circuits

    Publication Year: 1972, Page(s):21 - 30
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1888 KB)

    A systematic approach to the location of a single failure in a combinational logic network is presented. The method utilizes only the required tests and needs no fault table. The structure of the logic network is taken into consideration when selecting the tests to be applied. For tree networks, we start from the gate that generates a primary output and sequentially trace back through the stages o... View full abstract»

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  • Multiple Fault Detection in Combinational Networks

    Publication Year: 1972, Page(s):31 - 36
    Cited by:  Papers (44)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1296 KB)

    Combinational networks with no internal fan-out are considered from the point of view of testing for multiple faults. Several different approaches utilizing added inputs and observable outputs are considered and the tradeoffs are discussed. View full abstract»

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  • Asynchronous Arbiters

    Publication Year: 1972, Page(s):37 - 42
    Cited by:  Papers (40)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (944 KB)

    When two or more processors attempt to simultaneously use a functional unit (memory, multiplier, etc.), an arbiter module must be employed to insure that processor requests are honored in sequence. The design of asynchronous arbiters is complicated because multiple input changes are allowed, and because inputs may change even if the circuit is not in a stable state. A practical arbiter and its imp... View full abstract»

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  • A Suggestion for a High-Speed Parallel Binary Divider

    Publication Year: 1972, Page(s):42 - 55
    Cited by:  Papers (22)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1808 KB)

    A family of four procedures to compute the inverse 1/X of a given binary number X normalized between 0.5 and 1 is described. The quotient is obtained in redundant binary form, i.e., in a base 2 code in which digits can assume any positive or negative integer value. All methods here described can be implemented by combinatorial networks; the dividers realized in this way are very fast because all c... View full abstract»

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  • A Nonlinear Feature Extraction Algorithm Using Distance Transformation

    Publication Year: 1972, Page(s):56 - 63
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1216 KB)

    Feature extraction has been recognized as a useful technique for pattern recognition. Feature extraction is accomplished by constructing a mapping from the measurement space to a feature space. Often, the mapping is chosen from an arbitrarily specified parametric family by optimizing the parameters with respect to a separability criterion. View full abstract»

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  • Universal Modules for Bounded Signal Fan-Out Synchronous Sequential Circuits

    Publication Year: 1972, Page(s):63 - 79
    Cited by:  Papers (8)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2392 KB)

    Universal modules are presented that can be used to realize any single input-single output synchronous sequential machine in the form of a circuit in which the input signal enters only one module. Additionally, no signal in the circuit fans out to more than some bounded number of terminals where the bound depends only on the module being used. Two different realization schemes are presented. The f... View full abstract»

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  • Generation of Fault Tests for Linear Logic Networks

    Publication Year: 1972, Page(s):79 - 83
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (880 KB)

    In this note we study the problem of fault detection in linear logic networks. We introduce the concept of error vectors that indicate how the effect of a fault propagates through a network. These vectors allow one to identify redundancies in the network as well as calculate the output of the network given a fault and an input. Problems related to fault diagnosis and the detection of multiple faul... View full abstract»

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  • On Generating Multipliers for a Cellular Fast Fourier Transform Processor

    Publication Year: 1972, Page(s):83 - 87
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (880 KB)

    One possible hardware implementation for the fast Fourier transform (FFT) of 2m samples is to have 2m-1 cells, each of which performs two of the necessary computations during each of the m passes through the processor. But in each of these m passes, each of the 2m-1cells may require a different multiplier coefficient for its computations. The two most obvious solutions are costly. The m... View full abstract»

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  • A Note on the Interruption of Extended Core Storage Transfers

    Publication Year: 1972, Page(s):87 - 90
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (760 KB)

    In the Control Data 6000 system transfers between central memory and extended core storage may be interrupted through the issuance of an exchange jump by a peripheral processor. Reinitiation of the transfer requires that it be repeated completely rather than resumed at the point of interruption. The transfer process locks out the central processing unit (CPU), so an interrupted trahsfer results in... View full abstract»

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  • Optimum Logic Modules

    Publication Year: 1972, Page(s):90 - 96
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1224 KB)

    The results of an exhaustive analysis undertaken to determine the optimum three-input logic modules are examined. The optimum logic module is restricted to realize all three-variable functions in two logic levels, with one polarity available for each input variable. Only one three-input logic module satsifies these restrictions for three variables. All realizations with the fewest logic modules an... View full abstract»

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  • Note on Minimal Congruences on Transition Graphs

    Publication Year: 1972, Page(s):96 - 97
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (432 KB)

    A new proof is given for the following fact: All minimal congruences on a transition graph are of one of four types and can easily be obtained by inspecting the graph. View full abstract»

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  • Some Notes on Speeding Up Certain Loops by Software, Firmware, and Hardware Means

    Publication Year: 1972, Page(s):97 - 100
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (864 KB)

    Some ways of speeding up certain loops by software, firmware, and hardware means are discussed in this note. The importance of the inner loop calculation is emphasized and a simple, though as yet unused, programming technique is presented whereby the inner loop time may be reduced by approximately 20 percent. The general problem of a program with many loops is then considered and a method is indic... View full abstract»

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  • Minimization of Fuzzy Functions

    Publication Year: 1972, Page(s):100 - 102
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (624 KB)

    It is shown that the minimum canonical sum-of-products form of a given fuzzy function is the union of all its prime implicants. A reduction rule, which is necessary and sufficient, is presented that will generate all the prime implicants. View full abstract»

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  • Functional Transformation in Simplification of Multivalued Switching Functions

    Publication Year: 1972, Page(s):102 - 105
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2016 KB)

    A concept of functional transformation of multivalued switching functions, used to obtain simplified implementations is presented. Given some function f, a transformed function g is generated from f by permuting some or all of the truth values. Then, implementing g and performing a reverse permutation, a simpler implementation for f is obtained. A P matrix technique is given to facilitate determin... View full abstract»

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  • Contributors

    Publication Year: 1972, Page(s):105 - 107
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  • B72-4 System/360 Job Control Language

    Publication Year: 1972, Page(s):108 - 109
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  • B72-2 A Compiler Generator

    Publication Year: 1972, Page(s): 109
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  • B72-3 Computer Structures, Readings and Examples

    Publication Year: 1972, Page(s):109 - 110
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  • B72-4 Expanding Use of Computers in the 70' Technology–Markets • Needs • Technology

    Publication Year: 1972, Page(s): 110
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  • Abstracts of Current Computer Literature

    Publication Year: 1972, Page(s):111 - 127
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org