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Computers, IEEE Transactions on

Issue 5 • Date May 1971

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Displaying Results 1 - 25 of 30
  • IEEE Transactions on Computers - Table of contents

    Page(s): c1 - 616
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    Freely Available from IEEE
  • IEEE Computer Society

    Page(s): c2
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    Freely Available from IEEE
  • Asynchronous Unit Delays

    Page(s): 493 - 499
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    This paper considers the problem of designing an n-input, n-output, asynchronous unit delay (AUD) [2], [7], [13]. In the general case, all input changes are allowed in an AUD. However, the restricted case where only single input changes are allowed has been investigated in detail. Starting with linear single error-correcting codes, an unusual method of obtaining a uniquely reduced flow table of a restricted AUD is developed. Such a reduced table has 2k substitution property (SP) partitions [15] on the set of internal states whose product is the zero partition, where k is the smallest integer equal to or greater than log2 n. Hence, the state behavior of an n-input n-output restricted AUD is realizable by 2k two-state sequential circuits connected in parallel [15]. A direct algorithm for obtaining this realization is also given. View full abstract»

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  • On Delayed-Input Asynchronous Sequential Circuits

    Page(s): 500 - 503
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    This paper presents an alternate approach to the problem of delayed-input circuit realization of any fundamental mode asynchronous flow table. This approach is based on partition theory. It is shown that an equivalent normal primitive flow table of any reduced flow table has n binary partitions with substitutioh property such that their product is a 2nblock partition with substitution property, where n is the number of binary inputs. Such a property leads directly to a circuit which realizes the flow table and is a serial connection of two smaller subcircuits. The first subcircuit is again decomposable into n smaller circuits connected in parallel. It is shown that these n circuits always correspond to trivial delays in the input lines, thus leading to the delayed-input circuit realization of the fundamental mode flow table. View full abstract»

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  • Batch-Fabricated Three-Dimensional Planar Coaxial Interconnections for Microelectronic Systems

    Page(s): 504 - 511
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    A batch-fabricated three-dimensional coaxial microelectronic interconnection and packaging technique has been developed that is particularly suited to semiconductor chips of all complexities, ranging from single-junction devices to large-scale integrated circuit devices. The interconnections are coaxial in three dimensions, are formed by electrochemically sculpturing copper planes, and are assembled by pressure-stacking the planes to combinatorially interconnect, mount, and remove heat from high-density semiconductor systems. Although initially developed for high-speed digital systems, the technique is generally universally applicable to other disciplines, such as microwave circuits and structures. Circuit and semiconductor chip package densities can be achieved which offer one to three orders of magnitude increased density over conventional packaging systems. The technique is believed the closest to a truly three-dimensional interconnect medium yet achieved that can be nondestructively disassembled for repair, that has the thermal management capabilities required for high-density systems, and that is free of interconnection crosstalk. View full abstract»

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  • Computer-Aided Preliminary Layout Design of Customized MOS Arrays

    Page(s): 512 - 523
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    One of the most perplexing problems confronting device designers utilizing MOS technology is the development of an effective layout design methodology. This paper describes a versatile layout design scheme for customized digital-type MOS arrays utilizing four-phase clocking schemes (ratioless logic). The analytical characterization of this layout design scheme is defined through the introduction of p-order and m-order indices. The p-order indices are assigned to members of the Boolean equation set that define the relative placement of their mechanization areas (p-diffusion structures) on the MOS array. The m-order indices are assigned to members of the term set that define their relative placements within parallel metalization channels on the MOS array. The underlying variables influencing the algorithmic derivation of quasi-optimal p-order and m-order assignments are also discussed. View full abstract»

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  • Fault Detection in Iterative Logic Arrays

    Page(s): 524 - 535
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    Kautz has studied the problem of testing one-and two-dimensional arrays of combinational cells under the assumptions that all cell inputs must be applied to a cell to test it completely and that a fault in a cell may cause any arbitrary change in its outputs. In this paper we study the same problem under a more restricted set of assumptions: 1) all faults in a cell can be detected by a known set of inputs (usually smaller than the set of all inputs); and 2) each fault will affect the cell outputs in a known manner. Necessary and sufficient conditions for detection of faults in one-dimensional arrays are obtained. A procedure for deriving efficient tests for one-dimensional arrays is presented. Sufficient conditions for the testability of two-dimensional arrays and procedures for constructing tests for some arrays are obtained. View full abstract»

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  • N-Fail-Safe Logical Systems

    Page(s): 536 - 542
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    The analysis and synthesis of the fail-safe logical systems have been studied by many authors. They utilize logical elements with asymmetric failure. It is shown that by duplicating two identical systems in parallel it is possible to raise the reliability of the system considerably. If, for example, 0 is the safe value, the duplicate output (0, 1) or (1, 0) is regarded as 1. The output (0, 0) is regarded as 0, which cannot, however, be judged to be correct or to be incorrect. View full abstract»

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  • Complementary Two-Way Algorithms for Negative Radix Conversions

    Page(s): 543 - 550
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    This paper describes two sets of algorithms in positive radix arithmetic for conversions between positive and negative integral radix representation of numbers. Each set consists of algorithms for conversions in either direction; these algorithms are mutually complementary in the sense they involve inverse operations depending upon the direction of conversion. The first set of algorithms for conversion of numbers from positive to negative radix (negative to positive radix) proceeds serially from the least significant end of the number and involves complementation and addition (subtraction) of unity on single-digit numbers. The second set of algorithms for conversion of numbers from positive to negative radix (negative to positive radix) proceeds in parallel starting from the full number (the most significant end of the number) and involves complementation and right (left) shift operations. The applications of these algorithms to integers, mixed integer-fractions, floating-point numbers, and for real-time conversions are given. View full abstract»

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  • Local Properties of Binary Images in Two Dimensions

    Page(s): 551 - 561
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    Aspects of topology and geometry are used in analyzing continuous and discrete binary images in two dimensions. Several numerical properties of these images are derived which are " locally countable." These include the metric properties area and perimeter, and the topological invariant, Euler number. "Differentials" are defined for these properties, and algorithms are given. The Euler differential enables precise examination of connectivity relations on the square and hexagonal lattices. Easily computable binary image characterizations are introduced, with reference to a serial binary image processor (BIP) now being built. A precise definition of "localness" is given, and some implications for image computation theory are examined. View full abstract»

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  • Edge and Curve Detection for Visual Scene Analysis

    Page(s): 562 - 569
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    Simple sets of parallel operations are described which can be used to detect texture edges, "spots," and "streaks" in digitized pictures. It is shown that, by comparing the outputs of the operations corresponding to (e.g.,) edges of different sizes, one can construct a composite output in which edges between differently textured regions are detected, and isolated objects are also detected, but the objects composing the textures are ignored. Relationships between this class of picture processing operations and the Gestalt psychologists' laws of pictorial pattern organization are also discussed. View full abstract»

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  • On the Fast Fourier Transform on Finite Abelian Groups

    Page(s): 569 - 571
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    Recent work, apparently beginning with a paper by Welch in 1966, has shown that character expansions on finite Abelian groups can be fast computed in a way that makes the FFT and FWT special cases. It is shown here how the computational saving depends on the annihilator subgroup of the character group under consideration. View full abstract»

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  • Large-Scale Circuit Interconnection for Boolean Function Implementation

    Page(s): 572 - 575
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    The efficient production of LSI realizations of Boolean functions is studied and two interconnection procedures are presented. The first procedure is a modular method using planar circuits. The second procedure, which stresses a minimum number of gates, results in an "all purpose" chip which can be personalized externally by the customer. View full abstract»

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  • An Algorithm for Pattern Classification Using Eigenvectors

    Page(s): 575 - 578
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    An algorithm for pattern classification using eigenvectors is presented. This algorithm provides an alternative viewpoint for obtaining a solution weight vector of certain pattern classification problems. Convergence of the algorithm is proved and the termination condition of iteration is given. An interesting point is that this algorithm does not require the inversion of matrices, instead it requires the computation of eigenvalues and eigenvectors of the matrix. View full abstract»

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  • An Algebraic Proof of the Paull–Unger Theorem

    Page(s): 578 - 580
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    The principal result of Paull and Unger on incomplete machine minimization is given an algebraic setting whereby an analogy with the classical minimization theory for Boolean functions is exhibited. View full abstract»

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  • On Autonomous NOR Sequential Machines

    Page(s): 580 - 582
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    This note considers the analysis of autonomous NOR sequential machines from a linear machine point of view. It is shown that, under certain conditions, the techniques developed for linear machines are directly applicable to NOR machines. View full abstract»

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  • Measures of Op-Code Utilization

    Page(s): 582 - 584
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    The static and dynamic utilization of a set of machine op-codes is examined. Two measures of the effective use of machine instructions are discussed and applied to samples of hand-coded programs and object code. View full abstract»

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  • Halftone Images Using Computer Graphics

    Page(s): 584 - 585
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    A new method is described for producing pictorial output directly from digitized density values. The output is recorded on a high-resolution microfilm printer and can be obtained in normal computer turnaround time. Where high-quality pictures are required, the system displays a definite advantage over line printer output. View full abstract»

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  • Comments on "Nonlinear Sequential Circuits"

    Page(s): 585 - 586
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    This correspondence describes a way to find the co-efficients of the polynomials which were used to represent nonlinear sequential circuits.1 View full abstract»

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  • Comments on "Universal Logic Modules and Their Applications"

    Page(s): 586 - 587
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    Research on universal logic modules has taken place with two directed aims: 1) the production of universal microcircuits, and 2) the design of adaptive logic systems. This correspondence comments on the progress in these two fields. View full abstract»

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  • Author's Reply2

    Page(s): 587
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    My paper "Negative Radix Conversion," contained the only reference known to me at the time [1]. View full abstract»

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  • Comment on "An Algorithm for a Fast Hadamard Matrix Transform of Order Twelve"

    Page(s): 587 - 588
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    A recently proposed matrix factorization for a Hadamard matrix of order twelve is shown to be invalid in that the factored matrix is not Hadamard. View full abstract»

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  • Author's reply3

    Page(s): 588
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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Editor-in-Chief
Albert Y. Zomaya
School of Information Technologies
Building J12
The University of Sydney
Sydney, NSW 2006, Australia
http://www.cs.usyd.edu.au/~zomaya
albert.zomaya@sydney.edu.au