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IEEE Transactions on Computers

Issue 4 • Date April 1971

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Displaying Results 1 - 25 of 30
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1971, Page(s):c1 - 492
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    Freely Available from IEEE
  • IEEE Computer Society

    Publication Year: 1971, Page(s): c2
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    Freely Available from IEEE
  • Editor's Notice

    Publication Year: 1971, Page(s): 381
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    Freely Available from IEEE
  • State Assignments for Asynchronous Sequential Machines

    Publication Year: 1971, Page(s):382 - 391
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2016 KB)

    In this paper, a heuristic state assignment algorithm for asynchronous sequential machines is presented. Machines realized by this assignment scheme will result in circuits having a small amount of gate inputs and operating in single transition time. It is also shown that for a flow table having m1input columns, m input variables, and d stable states, the number of gate inputs required ... View full abstract»

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  • Failure-Tolerant Sequential Machines with Past Information

    Publication Year: 1971, Page(s):392 - 396
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (936 KB)

    A sequential machine must have certain redundant information in order to be capable of correcting error. As past inputs and past states are redundant, a sequential machine with error correction capability is constructable by making use of these elements of past information. This paper describes conditions of state assignments, numbers of required redundant state variables, and estimation of reliab... View full abstract»

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  • Contextual Word Recognition Using Binary Digrams

    Publication Year: 1971, Page(s):397 - 403
    Cited by:  Papers (16)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1464 KB)

    This paper describes a special-purpose character recognition system which uses contextual information for the recognition of words from any given dictionary of words. Previous techniques that utilized context involved letter transition probabilities of digrams and trigrams. This research introduces the concept of binary digrams which overcomes some of the problems of past approaches. They can be u... View full abstract»

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  • A Computing Machine Based on Tree Structures

    Publication Year: 1971, Page(s):404 - 418
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3112 KB)

    The expenditure of resources to provide via software more structure and more function in conventional machines has become excessive. The answer to this problem may consist in providing more structure and more function in hardware. With respect to structure, we describe 1) the binary tree as basic data and control structure, 2) the implementation of a binary tree by a conventional memory, and 3) th... View full abstract»

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  • On the Design of Universal Boolean Functions

    Publication Year: 1971, Page(s):418 - 423
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1152 KB)

    A Boolean function U( z1,...,zm) is universal for given n≥1 and a set I of variables if it realizes all Boolean functions f(x1,..., xn) by substituting for each zj a variable of I. Designs of universal Boolean functions for various specifications of I are considered for the practical cases of n<10. Assuming the number m of input terminals as cri... View full abstract»

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  • Alternative Algorithm for Hilbert's Space-Filling Curve

    Publication Year: 1971, Page(s):424 - 426
    Cited by:  Papers (54)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB)

    An algorithm for generating Hilbert's space-filling curve in a byte-oriented manner is presented. In the context of one application of space-filling curves, the algorithm may be modified so that the results are correct for continua rather than for quantized spaces. View full abstract»

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  • A Characterization of Some Asynchronous Sequential Networks and State Assignments

    Publication Year: 1971, Page(s):426 - 436
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2440 KB)

    An asynchronous sequential network is an interconnection of several asynchronous sequential circuits. Asynchronous networks are classified according to the relative time delay of the individual circuit's feedback signals and input signals. They are also classified by the manner in which the circuits interact. In addition, another network model uses duplicate paths for the feedback signals and the ... View full abstract»

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  • Pulse Input Asynchronous Sequential Circuits

    Publication Year: 1971, Page(s):436 - 442
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1528 KB)

    Traditionally, synchronous sequential circuits are considered controlled by input pulses, and asynchronous sequential circuits by input levels. The aim of this note is to study the general properties of a class of asynchronous circuits with some inputs that can be thought of as driven by "pulses." The synthesis process and the internal structure of these circuits, called pulse input asynchronous s... View full abstract»

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  • A 40-ns 17-Bit by 17-Bit Array Multiplier

    Publication Year: 1971, Page(s):442 - 447
    Cited by:  Papers (63)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3368 KB)

    A high-speed array multiplier generating the full 34-bit product of two 17-bit signed (2's complement) numbers in 40 ns is described. The multiplier uses a special 2-bit gated adder circuit with anticipated carry. Negative numbers are handled by considering their highest order bit as negative, all other bits as positive, and adding negative partial products directly through appropriate circuits. T... View full abstract»

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  • Probabilistic Automata with Monitored Final State Sets

    Publication Year: 1971, Page(s):448 - 452
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (960 KB)

    Probabilistic automata with time-variant final state sets monitored, in an intuitive manner, by autonomous probabilistic automata are considered. It is shown that they include a scheme suggested by Turakainen as a particular case, and that they accept all the stochastic languages. If the monitors are started in stationary distributions, it is proved that such schemes will accept all and only the s... View full abstract»

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  • Single-Parameter Solutions for Flip-Flop Equations

    Publication Year: 1971, Page(s):452 - 454
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    General one-parameter solutions are exhibited for the RS, RST, and JK flip-flop input equations. View full abstract»

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  • The Further Reduction of CC-Tables

    Publication Year: 1971, Page(s):454 - 456
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    Paull and Unger [1] were the first to develop methods for solving the problem of minimizing the number of internal states of incompletely specified sequential machines. Grasselli and Luccio [2] improved upon these methods by introducing rules for reducing the size of the problem and by transforming the problem into a linear integer programming problem. House and Stevens [3] have provided a means o... View full abstract»

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  • General Shift-Register Sequences of Arbitrary Cycle Length

    Publication Year: 1971, Page(s):456 - 459
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (936 KB)

    An r-ary shift-register sequence is desired that has arbitrary cycle length L≤rkfor arbitrary r and k, where k is the number of stages (degree) of the shift register. The existence of such sequences is established for "almost all" cycle lengths L. Furthermore, existence of such sequences which are "zero free" for almost all cycle lengths L is proved. View full abstract»

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  • On the Delay Required to Realize Boolean Functions

    Publication Year: 1971, Page(s):459 - 461
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    Using as logic modules two-input one-output arbitrary logic gates, this note considers the problem of the longest chain (number of levels) in a tree-type interconnection realizing a Boolean function of n variables. Specifically, we are interested in the minimum number of levels L(n) by which we can constructively realize all Boolean functions of n variables. It was previously shown that L(n)≤... View full abstract»

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  • A Graphical Method for Checking Complete Monotonicity

    Publication Year: 1971, Page(s):461 - 464
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    Complete monotonicity is a necessary condition for linear separability of a switching function and it is equivalent to the 2-asummable property. A test for this property using a tabular representation of a switching function and an easily generated test card is given. This method may be used reasonably well up to six variables. View full abstract»

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  • A Method of Solution for Multiple-Valued Logic Expressions

    Publication Year: 1971, Page(s):464 - 467
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (768 KB)

    A method of solving a system of simultaneous equations within a multiple-valued logic algebra is presented. View full abstract»

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  • On Universal Logic Primitives

    Publication Year: 1971, Page(s):467 - 469
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    A universal logic primitive (ULP) is a logic function by which every logic function can be composed. The total number of all ULPs and all nondegenerate ULPs for n logic variables is derived and a procedure for determining all of them is presented. View full abstract»

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  • Economical Iterative and Range-Transformation Schemes for Division

    Publication Year: 1971, Page(s):470 - 472
    Cited by:  Papers (2)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    It is shown that the Wilkes-Harvard and Newton-Raphson iterative division schemes with an order of convergence more than two or three are uneconomical for realization in computers. View full abstract»

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  • Generation of Right-Linear Grammars from Regular Expressions

    Publication Year: 1971, Page(s):472 - 473
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    A finite state language can be represented by a regular expression or a right-linear grammar. An algorithm to generate a right-linear grammar for regular expression is presented. The algorithm can be implemented on computers. A Snobol 4 program for this algorithm was written for the IBM 360/65 with success. View full abstract»

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  • Note on Circuits and Chains of Spread k in the n-Cube

    Publication Year: 1971, Page(s): 474
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    A known bound on the maximum size of a subset of the binary n-cube with distance k is applied to yield an asymptotically good bound on the length of a circuit or chain in the n-cube of spread k. View full abstract»

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  • A Two-Way Automaton with Fewer States than Any Equivalent One-Way Automaton

    Publication Year: 1971, Page(s):474 - 475
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    This correspondence presents an example of a two-way automaton which has significantly fewer states than any one-way automaton accepting the same set of tapes. Thus, in this particular case, memory space can be saved by using a two-way automaton. This savings in space, however, is accompanied by an increase in recognition time. View full abstract»

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  • Generation of Prime Implicants by Direct Multiplication

    Publication Year: 1971, Page(s):475 - 476
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    This correspondence shows that the Necula [1] and Slagle, Chang. and Lee [2] methods for determining prime implicants are a mechanization of a method first given by Nelson [3], i. e., generating of all prime implicants by direct expansion of a conjunctive form to a disjunctive form. View full abstract»

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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org