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Computers, IEEE Transactions on

Issue 2 • Date Feb. 1971

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Displaying Results 1 - 25 of 28
  • IEEE Transactions on Computers - Table of contents

    Page(s): c1 - 260
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    Freely Available from IEEE
  • IEEE Computer Society

    Page(s): c2
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    Freely Available from IEEE
  • Degrees of Freedom and Modular Structure in Matrix Multiplication

    Page(s): 133 - 141
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    An algorithm is presented which enables certain matrix multiplications in a digital computer to be implemented with a considerable savings in storage and computational operations. For NxN matrix vector multiplication (that is a multiplication of a matrix by a vector) a maximum of N Σn-1 r=0 pr, storage words are necessary compared to normal full matrix storage requirements of N2locations. In addition only N Σn-1 r=0 Pr, computer operations are necessary compared to N2operation in a general vector matrix multiplication. N is chosen to be a highly composite number, N= πn-1 r=0 pr, and the pr, are integers. The algorithm takes advantage of the redundancies in the definition of certain matrices and develops a matrix description based on the number of degrees of freedom necessary in defining an NxN matrix. The algorithm is optimal in the sense that it describes a vector matrix multiplication in exactly as many operations as available degrees of freedom N σn-1 r=0 Pr(no greater number of degrees of freedom could be implemented in fewer operations). The matrix transformation formulation is based largely on noting the use of lexicographic positional digit notation in keeping track of the few parameters describing the final N by N matrix. The algorithm includes the generation of the fast Fourier transform, fast Hadamard transform, fast Walsh transform, fast Kronecker matrix transform, and an infinite class of transformations unnamed but potentially useful in generalized spectral analysis as well as coding, bandwidth reduction, and feature selection. View full abstract»

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  • Algebraic Fault Analysis for Constrained Combinational Networks

    Page(s): 141 - 148
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    A sequential machine that processes its inputs without changing state can be represented as a constrained combinational network. A system of Boolean equations that represent such a network must include assertions that formalize the required constraints. These constraints can be expressed as assertions about certain gate inputs and certain gate outputs within the network. In such networks, redundant and partially redundant gates are not pathological. The fault analysis method presented provides for the testing of both sides of an irredundant gate and for the detectable side of a partially redundant gate. View full abstract»

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  • Ambiguity in Graphs and Expressions

    Page(s): 149 - 153
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    A regular expression is called unambiguous if every tape in the event can be generated from the expression in one way only. The flow-graph technique for constructing an expression is shown to preserve ambiguities of the graph, and thus, if the graph is that of a deterministic automaton, the expression is unambiguous. A procedure for generating a nondeterministic automaton which preserves the ambiguities of the given regular expression is described. Finally, a procedure for testing whether a given expression is ambiguous is given. View full abstract»

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  • Parallel Processing with the Perfect Shuffle

    Page(s): 153 - 161
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    Given a vector of N elements, the perfect shuffle of this vector is a permutation of the elements that are identical to a perfect shuffle of a deck of cards. Elements of the first half of the vector are interlaced with elements of the second half in the perfect shuffle of the vector. View full abstract»

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  • Modular LSI Control Logic Design with Error Detection

    Page(s): 161 - 166
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    This paper describes a modular approach of implementing the control circuitry. It is achieved by the use of multifunctional binary decoder circuits in conjunction with a transistor array high-speed READ-ONLY memory. View full abstract»

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  • Two Approaches for Increasing Storage Density in Modern Digital Computing Systems

    Page(s): 167 - 175
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    Modern digital computing systems are primarily limited in how densely information may be recorded on the magnetic storage elements by the manner in which the information is retrieved (detected) from these storage facilities. Current systems store information at a density around 1000 bits per inch (bit/in); system elements, other than the detection process, could easily handle densities in excess of 3000 bit/in. This paper describes the signal present at the output of the read-write head and suggests two systems by which detection at high bit densities may be accomplished. The error rate associated with each system is given and the results are applied to a computer system using a magnetic disk file as the storage element. It is demonstrated that these detection procedures can meet the widely accepted standard of one error in one billion bits at reasonable signal-to-noise ratios. View full abstract»

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  • An Algorithm for Finding Intrinsic Dimensionality of Data

    Page(s): 176 - 183
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    An algorithm for the analysis of multivariant data is presented along with some experimental results. The basic idea of the method is to examine the data in many small subregions, and from this determine the number of governing parameters, or intrinsic dimensionality. This intrinsic dimensionality is usually much lower than the dimensionality that is given by the standard Karhunen-Loève technique. An analysis that demonstrates the feasability of this approach is presented. View full abstract»

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  • The Avoidance and Elimination of Function Hazards in Asynchronous Sequential Circuits

    Page(s): 184 - 189
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    Armstrong et al.[1] have shown how critical races and function hazards can be suppressed in asynchronous sequential circuits by using gate delays to advantage rather than introducing explicit delay elements, if certain delay assumptions are satisfied. This paper shows that the same techniques may be used to design circuits which will respond reliably to simultaneous changes of several input variables. View full abstract»

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  • Periodic Representations and T-Partitionable Equivalents of Sequential Machines

    Page(s): 190 - 198
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    This paper deals with the problem of finding nontrivial periodic representations, with not necessarily null transient duration, of deterministic sequential machines. The well-known results in this area, based on means of d-equivalence partitions or regular d-partitions on the set of internal states of a sequential machine A, are generalized. Apart from this, the problem of finding nontrivial periodic representations of A is solved here by the well-known methods of input-independent partitions on the set of internal states of A and by the operation of the (τ, T) numeration introduced here. View full abstract»

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  • A Realizable Model for Stochastic Sequential Machines

    Page(s): 199 - 204
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    A new model for stochastic sequential machines is introduced. This model consists of a deterministic Mealy-type synchronous sequential machine some of whose inputs are random number generators while the outputs of another set of random number generators are used to perturb the output function of the deterministic Mealy machine. Thus this model is physically realizable in terms of random number generators, logic and memory elements. It is shown that this model and the Shannon model of a stochastic sequential machine are coextensive and a procedure is given, through a proof of this result, for obtaining one from the other. The model given here is then compared with the realizable model introduced by Nieh and Carlyle [1] and it is shown that their model and ours may be realized with identical random number generators for the case of input-state calculable stochastic sequential machines. View full abstract»

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  • Complexity of Partially Defined Combinational Switching Functions

    Page(s): 204 - 208
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    The complexity of the switching networks necessary to realize arbitrary combinational functions is studied. Asymptotic upper and lower bounds for fully defined functions are well known, while lower bounds also exist for partially defined combinational functions. The present paper supplements these results with the upper bounds for the partially defined functions. The results have possible relevance to pattern recognition. View full abstract»

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  • Hybrid Computer Solution of Optimal Control Problems

    Page(s): 209 - 211
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    This paper discusses limitations which arise when a method proposed by Miura et al. [1] is used for solving certain two-point boundary value problems on the hybrid computer. It is shown that the method proposed in [1] will not work in all cases. An example where the method fails is given. However, to emphasize the basic elegance and usefulness of this method, an extension to cover a more general target set is also introduced. View full abstract»

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  • A Simplified Definition of Walsh Functions

    Page(s): 211 - 213
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    A simple method is presented which defines Walsh functions in terms of products of Rademacher functions, but which preserves the ordering of the Walsh functions necessary to retain the notion of increasing number of zero crossings, or sequency. View full abstract»

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  • A Simple Postcorrection for Nonrestoring Division

    Page(s): 213 - 214
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    The nonrestoring division algorithm offers the advantages of speed and logical simplicity when working with signed, two's-complement binary numbers. The algorithm does not assure sign agreement between the calculated quotient and remainder, however, which is a disadvantage in some applications. This paper describes a postcorrection that will force sign agreement between quotient and remainder. The corrective operation is very simple to implement, especially in microprogrammed arithmetic units. View full abstract»

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  • An Iterative Array for Multiplication of Signed Binary Numbers

    Page(s): 214 - 216
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    An iterative array for multiplication of signed binary numbers is described. It uses controlled adder-subtractor cells. The negative numbers are in two's complement form and the product, if negative, is also available in this form without requiring any additional operations. View full abstract»

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  • Interactive Use of Problem Knowledge for Clustering and Decision Making

    Page(s): 216 - 222
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    An approach to clustering and decision making is presented where a prior problem knowledge is inserted interactively. The problem knowledge inserted is in the form of subcategory mean vectors and covariance matrices and in the expert's confidence that these means and covariances accurately characterize the category. Then observations of patterns from the category are used to update these a priori supplied means and covariances. The extent to which new observations update the a priori values depends upon the expert's a priori confidence. View full abstract»

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  • The Accelerated Relaxation Method for Linear Inequalities

    Page(s): 222 - 225
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    An algorithm called the accelerated relaxation method for finding a solution of a set of inequalities is given. Experimental results show that the accelerated relaxation method is far more efficient than the relaxation method, the fixed increment method, and the generalized-inverse Ho-Kashyap algorithm. View full abstract»

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  • Generation of a Clock Pulse for Asynchronous Sequential Machines to Eliminate Critical Races

    Page(s): 225 - 226
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    A circuit for generating a clock pulse for asynchronous circuits is given, and when used with transition sensitive flip-flops eliminates critical races for an arbitrary state assignment. Thus the minimum number of internal variables may be used. Furthermore, logic and sequential hazards will not affect the circuit performance. View full abstract»

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  • High Speed Generation of Maximal Length Sequences

    Page(s): 227 - 229
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    The construction described in this note makes possible the generation of any given linear shift register sequence of maximal period p= 2n-1, at a rate k times faster than the shift pulse rate. The construction is valid for any positive integer k which is not a multiple of p and it employs at most k linear shift registers of degree n or less. View full abstract»

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  • An Improved Method of Prime C-Class Derivation in the State Reduction of Sequential Networks

    Page(s): 229 - 231
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    The state reduction of sequential networks is achieved by selecting a minimal set of prime C-classes satisfying the cover and closure requirements. The derivation of all the C-classes and subsequent prime C-classes has been illustrated by Grasselli and Luccio [1] and relies on maximal C-class decomposition. In this note, an alternative method for deriving the prime C-classes is described. The method does not involve the maximal C-classes and is algorithmically easier to implement. View full abstract»

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  • A Note on the Solution of Sequential Boolean Equations

    Page(s): 231 - 234
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    The problem of solving sequential Boolean equations is examined in terms of nondeterministic finite transducers. An upper bound for the delay is established and a method for obtaining a deterministic equivalent is described. View full abstract»

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  • Topological Solution of Bilateral Switching Networks

    Page(s): 234 - 238
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    A method is described for synthesizing bilateral switching networks using a topological solution that does not employ algebraic or linear graph techniques. Using the eye as a pattern detector, one may trace an optimum path directly on the truth table from the input to the one or more desired outputs. This method overcomes many of the difficulties that have been encountered with relay contact logic, and at the same time helps the logician seek a planar symmetrical solution thaat is so desirable for monolithic circuits composed of MOS (metal-oxide semiconductor) devices. View full abstract»

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  • A Remark on the Concepts of Input-Memory and Output-Memory of Sequential Machines

    Page(s): 239
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    The definitions of input-memory and output-memory of a sequential machine are examined and an attempt is made to clarify some, confusion in the literature regarding the concepts of input-memort and output-memory. View full abstract»

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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Albert Y. Zomaya
School of Information Technologies
Building J12
The University of Sydney
Sydney, NSW 2006, Australia
http://www.cs.usyd.edu.au/~zomaya
albert.zomaya@sydney.edu.au