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IEEE Transactions on Computers

Issue 12 • Date Dec. 1971

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Displaying Results 1 - 25 of 47
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1971, Page(s):c1 - 1637
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    Freely Available from IEEE
  • IEEE Computer Society

    Publication Year: 1971, Page(s): c2
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    Freely Available from IEEE
  • Asynchronous Sequential Switching Circuits with Unrestricted Input Changes

    Publication Year: 1971, Page(s):1437 - 1444
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1768 KB)

    The problem of designing asynchronous circuits where the changes in binary input signals occur independently of one another is discussed. If several input changes occur within some interval δ1, the circuit behaves as though the changes were simultaneous. If consecutive changes are spaced by intervals exceeding some longer interval δ2 then the circuit reacts as though a sequence of single... View full abstract»

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  • Computer-Aided Synthesis or Multiple-Output Multilevel NAND Networks witk Fan-in and Fan-out Constraints

    Publication Year: 1971, Page(s):1445 - 1455
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1816 KB)

    A straightforward efficient computer algorithm for synthesizing multiple-output NAND (NOR) switching networks is presented which takes practical fan-in and fan-out limitations of logic gates into account. The algorithm is highly iterative and hence is very suitable for realizing large-size switching functions by a digital computer. The algorithm has been programmed in Fortran and a great deal of s... View full abstract»

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  • A Heuristic Procedure for the Partitioning and Mapping of Computer Logic Graphs

    Publication Year: 1971, Page(s):1455 - 1462
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1616 KB)

    A heuristic procedure for partitioning or mapping a set of interconnected blocks into subsets called modules is presented. Each module may be constrained in terms of the number of blocks and/or the number of intermodule connections that it can accommodate. The procedure allows given blocks to be mapped to more than one module in order to reduce the number of modules required if such reduction is d... View full abstract»

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  • Designing Sets of Fault-Detection Tests ror Combinational Logic Circuits

    Publication Year: 1971, Page(s):1463 - 1469
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1456 KB)

    This paper is concerned with the problem of determining, by means of terminal experiments, whether a given combinational switching circuit operates correctly or is impaired by some malfunction. We shall be primarily concerned with permanent faults due to component failures. It is assumed that other methods will be employed to protect the circuit against the effects of transient faults. A procedure... View full abstract»

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  • On a Pin Versus Block Relationship For Partitions of Logic Graphs

    Publication Year: 1971, Page(s):1469 - 1479
    Cited by:  Papers (338)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2056 KB)

    Partitions of the set of blocks of a computer logic graph, also called a block graph, into subsets called modules demonstrate that a two-region relationship exists between P, the average number of pins per module, and B, the average number of blocks per module. In the first region, P = KBr, where K is the average number of pins per block and 0.57 ≤ r ≤ 0.75. In the second region, that ... View full abstract»

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  • Iterative Arrays ror Radix Conversion

    Publication Year: 1971, Page(s):1479 - 1489
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1704 KB)

    the general study of the conversion of a number from the radix p to the radix q number system leads to four different algorithms for integers, and to four similar ones for fractions. Most transform algorithms can be implemented by iterative arrays of cells characterized by simple equations. Such arrays are very attractive with present-time large-scale integration technology. View full abstract»

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  • A Generalized Record Organization

    Publication Year: 1971, Page(s):1490 - 1495
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1176 KB)

    A generalized record organization is proposed from which many flxed and variable length records of hierarchical and network formats can be derived. In developing the generalization, attempts are made to characterize the record organization. By identifying the characteristics of the record organization, it is possible to segregate, for storage, the global record structural information from the loca... View full abstract»

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  • A Nand Model ror Fault Diagnosis in Combinational Logic Networks

    Publication Year: 1971, Page(s):1496 - 1506
    Cited by:  Papers (45)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2528 KB)

    A network model colled the normal NAND model is introduced for the study of fault diagnosis in combinational logic circuits. It is shown that every network can be transformed into an equivalent normal NAND network from which all the information pertaining to the diagnosis of the original network con be obtained. The use of this model greatly simplifies fault analysis and test generation. View full abstract»

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  • On Realizations of Boolean Functions Requiring a Minimal or Near-Minimal Number of Tests

    Publication Year: 1971, Page(s):1506 - 1513
    Cited by:  Papers (36)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1504 KB)

    This paper considers the design of combinational logic circuits which require a minimal or near-minimal number of tests. Bounds on the number of tests required by various network structures are considered. It is shown that for an n-input fanout-free network, the number of single and multiple fault detection test lies between 2 √n and n + 1, while the number of fault locations tests lies betw... View full abstract»

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  • Codes for Error Correction in High-Speed Memory Systems Part II: Correction of Temporary and Catastrophic Errors

    Publication Year: 1971, Page(s):1514 - 1520
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1096 KB)

    A few classes of codes, suitable for error correction in high-speed memory systems, are presented. The codes have relatively simple parallel decoding nets. The codes may be used for the correction of both temporary and catastrophic errors. View full abstract»

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  • Estimation of Classification Error

    Publication Year: 1971, Page(s):1521 - 1527
    Cited by:  Papers (32)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1120 KB)

    This paper discusses methods of estimating the probability of error for the Bayes' classifier which must be designed and tested with a finite number of classified samples. The expected difference between estimates is discussed. A simplifled algorithm to compute the leaving-one-out method is proposed for multivariate normal distributions wtih unequal co-variance matrices. The discussion is extended... View full abstract»

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  • An Interactive System for Reading Unformatted Printed Text

    Publication Year: 1971, Page(s):1527 - 1543
    Cited by:  Papers (14)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (8056 KB)

    A system intended to provide input of printed text to computers is applied to published patents, annotated law reports, and technical journals. View full abstract»

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  • Some Properties of Minimal Threshold Approximations

    Publication Year: 1971, Page(s):1544 - 1551
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1304 KB)

    In recent years, considerable interest has been given to the study of threshold logic. This interest stems primarily from the possible economic savings associated with the use of threshold elements in realizing arbitrary switching functions. Such realizations, for the most part, depend on successfully finding threshold functions that closely approximate the given function. Closeness of approximati... View full abstract»

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  • Computation of the Fast Fourier Transform from Data Stored in External Auxiliary Memory for Any General Radix r=2n, n ≥ 1

    Publication Year: 1971, Page(s):1552 - 1558
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (968 KB)

    A general method is presented for the computation of the fast Fourier transform from data stored in external auxiliary memory, for any general radix r = 2nn ≥e external data storage is necessitated whenever the internal computer memory is limited. The general radix requirement arises in the tradeoff in serial FFT processor machines, between the number of passes required to address... View full abstract»

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  • Pulse Reflection in Transmission Lines

    Publication Year: 1971, Page(s):1558 - 1563
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3152 KB)

    A simple theory based on linear approximation of the transient waveform and on the superposition theorem permits the prediction of waveforms and amplitude of the ripple voltage at the receiving end of a line which transmits pulses with finite rise time and which is mismatched at both ends. The influence of every connection in a digital system can be determined in this way. View full abstract»

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  • On Proving Sequential Machine Designs

    Publication Year: 1971, Page(s):1563 - 1566
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (832 KB)

    Based on a program-proving technique, a method for proving sequential machine designs is presented. The method associates with each state of the machine an assertion about the sequences taking the machine into that state. The design is proved by: showing all assertions true irrespective of state changes; and deriving the design specifications from the assertions at final states. The method is illu... View full abstract»

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  • The Organization and Use of Parallel Memories

    Publication Year: 1971, Page(s):1566 - 1569
    Cited by:  Papers (158)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (816 KB)

    As computer CPUs get faster, primary memories tend to be organized in parallel banks. The fastest machines now being developed can fetch of the order of 100 words in parallel. Unless memory and compiler designers are careful, serious memory conflicts and resulting performance degradation may result. Some of the important questions of design and use of such memories are discussed. View full abstract»

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  • On the Performance of Interleaved Memories with Multiple-Word Bandwidths

    Publication Year: 1971, Page(s):1570 - 1573
    Cited by:  Papers (9)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    Past studies of the performance of interleaved memory systems are extended in this note by adopting a more general model. The model assumes a system of N memory modules, each of which is made up of b submodules. Successive memory addresses are assigned to sequential submodules, modulo Nb. For increased effective memory bandwidth a so-called conflict buffer of size L + 1 is assumed to exist for sto... View full abstract»

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  • A Cellular-Array Multiplier for GF(2m)

    Publication Year: 1971, Page(s):1573 - 1578
    Cited by:  Papers (38)  |  Patents (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1168 KB)

    This note describes a cellular array that computes the product of two arbitrary elements of the Galois field GF(2m). The regularity of this array should make it attractive for LSI fabrication. View full abstract»

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  • Tapered Floating Point: A New Floating-Point Representation

    Publication Year: 1971, Page(s):1578 - 1579
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    It is well known that there is a possible tradeoff in the binary representation of floating-point numbers in which one bit of accuracy can be gained at the cost of halving the exponent range, and vice versa. A way in which the exponent range can be greatly increased while preserving full accuracy for most computations is suggested. View full abstract»

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  • Counting Responders in an Associative Memory

    Publication Year: 1971, Page(s):1580 - 1583
    Cited by:  Papers (30)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    A method of determining the number of responders to a search in an associative memory is presented. It is shown that less than one full adder per memory cell is required and that the maximum delay in establishing the count is proportional to n, where n is the log to the base 3 of the number of memory cells. View full abstract»

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  • Dynamic Resolution of Memory Access Conflicts

    Publication Year: 1971, Page(s):1583 - 1586
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB)

    This note presents a method for designing and implementing a dynamic priority assignment memory-access conflict-resolution circuit for use in multiprocessing systems with K processors. A decision rule which establishes the priority, assignment is given and an example which illustrates the techniques is also discussed. View full abstract»

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  • Right Shift for Low-Cost Multiply and Divide

    Publication Year: 1971, Page(s):1586 - 1589
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB)

    Although integrated-circuit technology promises to reduce the cost of logic, there are still situations where low-cost multiplication and/or division algorithms must be implemented in today's technology. This can be accomplished by the algorithms presented here: repetitive addition (subtraction) algorithms for multiplication (division), employing a right shift. The result of the operation is trunc... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org