By Topic

Computers, IEEE Transactions on

Issue 1 • Date Jan. 1971

Filter Results

Displaying Results 1 - 25 of 25
  • IEEE Transactions on Computers - Table of contents

    Page(s): c1 - 132
    Save to Project icon | Request Permissions | PDF file iconPDF (597 KB)  
    Freely Available from IEEE
  • IEEE Computer Society

    Page(s): c2
    Save to Project icon | Request Permissions | PDF file iconPDF (192 KB)  
    Freely Available from IEEE
  • New Editor-in-Chief

    Page(s): 1
    Save to Project icon | Request Permissions | PDF file iconPDF (1376 KB)  
    Freely Available from IEEE
  • Technical Paper Referees

    Page(s): 2 - 6
    Save to Project icon | Request Permissions | PDF file iconPDF (838 KB)  
    Freely Available from IEEE
  • A Binary Floating-Point Resistor

    Page(s): 7 - 11
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2544 KB)  

    The digital computer control of physical processes requires parameters that can be altered digitally. A resistor design is described that provides settings in a wide range with fixed precision. For this purpose a binary floating-point format is used both for expressing the resistor values and for the digital setting. A resistor structure is given that yields values expressed by the above format. Implementation employing electromechanical and electronic components is presented. The configuration described compares favorably with a straightforward binary design. It is expected that such a resistor will be especially useful for hybrid passive-network analyzer applications and, employed as a reference device, for the digital-to-analog and analog-to-digital conversion of other kinds of quantities. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimization and Simulation of Two Classes of Nonresetting Data Reconstructors

    Page(s): 12 - 18
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1096 KB)  

    This paper explores some new solutions to the problem of high-speed data reconstruction in real time. Two types of nonresetting data reconstructors are developed. Both types are simpler than the classical extrapolative hold circuits and when optimized give better performance. The optimization procedure is given and results of simulation studies are included. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Hybrid Computation Techniques Inferred from Functional Analysis

    Page(s): 19 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1496 KB)  

    The research reported in this paper is concerned with the use of functional analysis and operator theory in providing insights into iterative computational methods. The computational methods are discussed in the context of obtaining the closed-loop response of a complex feedback system on a hybrid computer. The need for iterative solution arises in problems in which the feedback cannot be computed instantaneously, for instance, when there are partial differential equations, and/or where there is a large number of arithmetic and logical operations. The tools of functional analysis are used to devise computational schemes with improved convergence properties. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Derivation of Minimal Complete Sets of Test-Input Sequences Using Boolean Differences

    Page(s): 25 - 32
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1680 KB)  

    This paper deals with a fault detection and diagnosis technique based on Boolean differences. A brief review of the notion of a Boolean difference is presented, and the concept of partial Boolean difference is introduced. An algorithm for obtaining minimal, complete sets of test-input sequences based on the partial Boolean differences of a switching function is formulated, and illustrations demonstrating the use of the technique are presented. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The FDP, a Fast Programmable Signal Processor

    Page(s): 33 - 38
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1456 KB)  

    This paper contains a description of the architecture of the fast digital processor (FDP), a general purpose digital attachment to a UNIVAC 1219 computer facility. The main purpose of the FDP is to enhance the capability of the UNIVAC facility for performance of digital signal processing operations such as digital filtering and discrete Fourier transforms. The structural design evolved during a series of discussions among the four authors. The FDP is presently being constructed under the supervision of one of the authors, P. McHugh, and should be completed in late 1970. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Data-Storage Format for Information System Files

    Page(s): 39 - 43
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1248 KB)  

    In developing its chemical information system, Chemical Abstracts Service (CAS) has built files which require hundreds of millions of bytes of storage and in which data elements may range in length from zero in one instance to several hundred bytes in another. To cope with this size and variability, CAS has developed an internal standardized storage format and has implemented it on the IBM System/360. This format, which is called Standard File Format (SFF), accommodates a mix of fixed-and variable-length data elements and permits the addition and deletion of data elements without affecting the program code. Symbolic addressing of data elements is achieved through the use of a directory within each record in the file. Implementation of standardized files has permitted the CAS system to operate with greater generality and flexibility. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Novel Parallel Binary Counter Design with Parity Prediction and Error Detection Scheme

    Page(s): 44 - 48
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1176 KB)  

    In binary counters, the parity bit is not preserved when the data undergo the counting operation. It is necessary to predict the parity bit that should be used with the correct result. A special design has been devised to share as much hardware as possible between the counter and the parity prediction circuit. This reduces the number of logic gates and gives a more efficient design. The scheme involves the use of the first 0 detection for both the counting operation and the parity prediction. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Synthesis of Networks with a Minimum Number of Negative Gates

    Page(s): 49 - 58
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2136 KB)  

    In this paper we develop an algorithm to design a switching network using only gates which represent negative functions. The number of gates in the network is minimized under the conditions that 1) the network consists of two levels, and 2) no fan-in restriction on each gate is imposed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimal Curve Fitting With Piecewise Linear Functions

    Page(s): 59 - 67
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1432 KB)  

    A method is described for determining an optimal straight-line segment approximation to specified functions for constrained and unconstrained endpoints. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Graph-Theoretical Methods for Detecting and Describing Gestalt Clusters

    Page(s): 68 - 86
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6768 KB)  

    A family of graph-theoretical algorithms based on the minimal spanning tree are capable of detecting several kinds of cluster structure in arbitrary point sets; description of the detected clusters is possible in some cases by extensions of the method. Development of these clustering algorithms was based on examples from two-dimensional space because we wanted to copy the human perception of gestalts or point groupings. On the other hand, all the methods considered apply to higher dimensional spaces and even to general metric spaces. Advantages of these methods include determinacy, easy interpretation of the resulting clusters, conformity to gestalt principles of perceptual organization, and invariance of results under monotone transformations of interpoint distance. Brief discussion is made of the application of cluster detection to taxonomy and the selection of good feature spaces for pattern recognition. Detailed analyses of several planar cluster detection problems are illustrated by text and figures. The well-known Fisher iris data, in four-dimensional space, have been analyzed by these methods also. PL/1 programs to implement the minimal spanning tree methods have been fully debugged. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The Realization of Polylinear Sequential Circuits Using Flip-Flop Memory

    Page(s): 87 - 94
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1832 KB)  

    In this paper there are developed simple processes for deriving, for finite synchronous sequential machines, polylinear sequential circuit realizations using trigger, set–reset, or J–K flip-flops as the memory elements. It is shown that each such realization is directly obtainable from a graph analogous to the reverse state diagram of the given machine; the latter graph was shown in a former paper by this author to correspond to a polylinear sequential circuit realization using delays for memory. The processes consist of the straightforward steps in the construction of the reverse state diagram analogs. Almost polylinear sequential circuits are defined, and it is shown how certain proper subgraphs of the aforementioned graphs can be used to derive these circuits. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Property of N-Graphs

    Page(s): 95 - 97
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (696 KB)  

    T. A. J. Nicholson has introduced a restricted class of drawn graphs (N-graphs) into the problem of drawing a graph with a minimum number of crosspoints. This short note shows some defects in representing the capability of N-graphs by presenting a planar graph which cannot be represented by any N-graphs. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Variable-Mode Counting with Straight Binary Counters

    Page(s): 97 - 98
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (552 KB)  

    A design technique using complementary gating and simulated data was developed to permit a straight binary counter to be used as a variable-mode counter. Any family of binary logic modules can be used. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Simulation Method for Computer Control Systems

    Page(s): 98 - 100
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (712 KB)  

    A computer control system simulation method utilizing two computers is presented. One is a control computer operating under almost actual conditions. The other is a multiprogrammed computer that simulates the plant. The time taken by the control computer to compute the control variables can be a function of the plant state. An optimum control example illustrating the application of the method is given. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Systems of Asynchronously Operating Modules

    Page(s): 100 - 104
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1080 KB)  

    This note considers the operation of systems composed of interconnected asynchronously operating modules and shows that some such systems may enter "blocking conditions" in which no module can change state. The model considered applies specifically to asynchronous systems in which each module is controlled only by its neighbors, but may also be relevant to other systems such as parallel computational schemes. We also demonstrate a procedure that may speed up computation and we show that the function computed by a given network may depend upon the initial state. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On the Time Necessary to Compute Switching Functions

    Page(s): 104 - 105
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB)  

    In this note we establish a new upper bound on the time to compute classes of switching functions. As did Shannon and Lupanov in their study of the number of elements necessary to compute switching functions, we base our method on a Shannon expansion about a certain number of variables of the function being computed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Minimization Technique for Tant Networks

    Page(s): 105 - 107
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (544 KB)  

    A TANT network is a three-level network composed solely of AND-NOT gates having only uncomplemented inputs. A method of minimal gate TANT realization of a Boolean function is presented. The procedure permits hand solution of four-and five-variable problems. A computer program will be required to handle more complex cases. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Conditional Interpretation of Operation Codes

    Page(s): 108 - 111
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (856 KB)  

    A method, called conditional interpretation, is proposed which will allow small computers to have as large a set of instructions as may be desired without using a large number of bits to hold the operation code. The method is based on the redundancy of machine language instruction sequences. Most machine language instructions have a limited number of "reasonable" successors. For example "load accumulator" hardly ever follows "enter accumulator." It turns out that if each instruction is allowed seven successors plus an "escape instruction," only about one out of every five instructions needs to be an "escape" to get to one of the less usual successors. Seventy-five percent of the time the desired "next instruction" is among the seven permitted successors. Since each instruction has its own, possibly unique, set of successors, the interpretation of the stored op-code is conditional upon the state of the machine. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Contributors

    Page(s): 112 - 114
    Save to Project icon | Request Permissions | PDF file iconPDF (4293 KB)  
    Freely Available from IEEE
  • Abstracts of Current Computer Literature

    Page(s): 115 - 132
    Save to Project icon | Request Permissions | PDF file iconPDF (5140 KB)  
    Freely Available from IEEE
  • Information for authors

    Page(s): 132
    Save to Project icon | Request Permissions | PDF file iconPDF (375 KB)  
    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Albert Y. Zomaya
School of Information Technologies
Building J12
The University of Sydney
Sydney, NSW 2006, Australia
http://www.cs.usyd.edu.au/~zomaya
albert.zomaya@sydney.edu.au