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IEEE Transactions on Computers

Issue 8 • Date Aug. 1970

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  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1970, Page(s):c1 - 782
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  • IEEE Computer Group

    Publication Year: 1970, Page(s): c2
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  • Preface

    Publication Year: 1970, Page(s):679 - 680
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  • A Formalization of Floating-Point Numeric Base Conversion

    Publication Year: 1970, Page(s):681 - 692
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2808 KB)

    The process of converting arbitrary real numbers into a floating-point format is formalized as a mapping of the reals into a specified subset of real numbers. The structure of this subset, the set of n significant digit base β floating-point numbers, is analyzed and properties of conversion mappings are determined. For a restricted conversion mapping of the n significant digit base δ num... View full abstract»

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  • The Correspondence Between Methods of Digital Division and Multiplier Recoding Procedures

    Publication Year: 1970, Page(s):692 - 701
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1856 KB)

    This paper relates previous analyses of the binary SRT division to the theory of multiplier recoding. Since each binary quotient digit has three possible values, the quotient resulting from the SRT division is in recoded form; in this paper it is shown that the recoding is a function of the divisor, and the method for determining the characteristic Boolean function of the recoding is presented. Th... View full abstract»

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  • On Division by Functional Iteration

    Publication Year: 1970, Page(s):702 - 706
    Cited by:  Papers (47)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (856 KB)

    In order to avoid the time delays associated with linearly convergent division based on subtraction, other iterative schemes can be used. These are based on 1) series expansion of the reciprocal, 2) multiplicative sequence, or 3) additive sequence convergent to the quotient. These latter techniques are based on finding the root of an arbitrary function at either the quotient or reciprocal value. A... View full abstract»

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  • High-Speed Computer Multiplication Using a Multiple-Bit Decoding Algorithm

    Publication Year: 1970, Page(s):706 - 709
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    This paper presents a method of performing the binary multiplication beyond the scheme of multiple ADD and SHIFT. The binary multiplication algorithm will be discussed first, followed by block decoding method, logic implementation, hardware consideration, and two examples which are at the end of the discussion. View full abstract»

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  • The LX-1 Microprocessor and Its Application to Real-Time Signal Processing

    Publication Year: 1970, Page(s):710 - 720
    Cited by:  Papers (17)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2280 KB)

    LX-1 is an integrated circuit prototype of a microprocessor which is being used as a design vehicle to study the problems associated with the design and implementation of a similar computer constructed with large-scale integrated circuits. The organizational simplicity of LX-1 is emphasized and the supporting microprogramming and simulation facilities are discussed and examples are given. View full abstract»

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  • Design of the Arithmetic Units of ILLIAC III: Use of Redundancy and Higher Radix Methods

    Publication Year: 1970, Page(s):720 - 733
    Cited by:  Papers (26)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2608 KB)

    In keeping with the experimental nature of the Illinois Pattern Recognition Computer (ILLIAC III), the arithmetic units are intended to be a practical testing ground for recent theoretical work in computer arithmetic. This paper describes the use of redundant number systems and the design of a structure with which multiplication and division are executed radix 256. The heart of the unit is the sto... View full abstract»

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  • A Universal Arithmetic Building Element (ABE) and Design Methods for Arithmetic Processors

    Publication Year: 1970, Page(s):733 - 745
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2224 KB)

    The advent of large-scale integration of logic circuits requires the definition of digital computer structure in terms of large functional arrays of logic of very few types. This paper describes a single-package arithmetic processor called the arithmetic building element (ABE). The ABE accepts operands in either conventional or signed-digit radix-r representation and produces signed-digit results,... View full abstract»

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  • Signed-Digit Division Using Combinational Arithmetic Nets

    Publication Year: 1970, Page(s):746 - 748
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB)

    To meet the challenge created by the advent of large- scale integration, a unique microelectronic arithmetic building element and combinational arithmetic nets, composed of the building elements, have been studied and proposed for arithmetic processor design. A fast division algorithm, particularly suitable for floating- point arithmetic, has also been developed for signed-digit arithmetic. This a... View full abstract»

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  • Adder With Distributed Control

    Publication Year: 1970, Page(s):749 - 751
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    An adder is described for addition of a large number of binary numbers xj, j=1, 2, ⋯, m, where xj=∑ixji⋅ 2i, xji=0, 1, i=0, 1, ⋯, n-1. The adder's algorithm has two parts: 1) the bits xjiare added independently for each binary order i:si=∑jxji≦m and the ... View full abstract»

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  • Binary Logic for Residue Arithmetic Using Magnitude Index

    Publication Year: 1970, Page(s):752 - 757
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1080 KB)

    We consider a residue number system using n pairwise relatively prime moduli m1,⋯,mnto represent any integer X in the range M/ 2≤X>M/2, when M = ∏mi. The moduli miare chosen to be of the 2-1 type, in order that the residue arithmetic can be implemented by means of binary registers and binary logic. Further, for each residue number X, a magnitud... View full abstract»

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  • On the Addition of Binary Numbers

    Publication Year: 1970, Page(s):758 - 759
    Cited by:  Papers (24)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    An upper bound is derived for the time required to add numbers modulo 2n, using circuit elements with a limited fan-in and unit delay, and assuming that all numbers have the usual binary encoding. The upper bound is within a factor (1 + ε) of Winograd's lower bound (which holds for all encodings), where ε→0 as n→∞, and only O(n log n) circuit elements are required. View full abstract»

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  • Contributors

    Publication Year: 1970, Page(s):760 - 761
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  • B70-3 Analog-to-Digital and Digital-to-Analog Conversion Techniques

    Publication Year: 1970, Page(s):762 - 763
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  • R70-25 Construction of Multistep Integration Formulas for Simulation Purposes

    Publication Year: 1970, Page(s):763 - 764
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  • R70-26 Probabilistic Aspects of Machine Decomposition Theory

    Publication Year: 1970, Page(s): 764
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  • R70-27 Tree Generating Regular Systems

    Publication Year: 1970, Page(s): 764
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  • R70-28 A Note on Definite Stochastic Sequential Machines

    Publication Year: 1970, Page(s):764 - 765
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  • R70-29 Uniform Synthesis of Sequential Circuits

    Publication Year: 1970, Page(s): 765
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  • R70-30 Fuzzy Logic and Its Application to Switching Systems

    Publication Year: 1970, Page(s): 766
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  • R-70-31 A Generalized Firing Squad Problem

    Publication Year: 1970, Page(s): 766
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  • Abstracts of Current Computer Literature

    Publication Year: 1970, Page(s):767 - 782
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  • Information for authors

    Publication Year: 1970, Page(s): 782
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org