IEEE Transactions on Computers

Issue 9 • Sept. 1969

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Displaying Results 1 - 19 of 19
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1969, Page(s):c1 - 884
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  • IEEE Computer Group

    Publication Year: 1969, Page(s): c2
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  • Editor's Notice

    Publication Year: 1969, Page(s): 785
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  • The Serial Solution of the Diffusion Equation Using Nonstandard Hybrid Techniques

    Publication Year: 1969, Page(s):786 - 799
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6752 KB)

    In the conventional approach to the serial solution of the one-dimension diffusion equation using continuous space-discrete time (CSDT) techniques, there is a large amount of positive feedback in the resultant analog programming. For all practical purposes, the presence of this positive feedback makes the conventional analog method useless. View full abstract»

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  • The ILLIAC IV Processing Element

    Publication Year: 1969, Page(s):800 - 816
    Cited by:  Papers (12)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3733 KB)

    This paper describes the design of the processing element (PE) of I IV, a parallel processing computer consisting of 256 PE's, each with an associated 2048 word memory. Each PE-memory combination with its data-dependent controls is a computer in itself, devoid of those controls common to all PE-memory combinations, such as instruction decoding, instruction look-ahead, etc. View full abstract»

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  • Threshold Gate Building Blocks

    Publication Year: 1969, Page(s):816 - 823
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1662 KB)

    The problem of choosing a standard circuit package with which to realize a given logic design can be solved for threshold logic design by the use of majority gates. However, the use of asymmetric threshold gates allows substantial improvements in the amount of logic done per signal pin of the circuit package. Examples are given, illustrating savings in logic design effort, total cost of integrated... View full abstract»

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  • Readily Programmable Procedures for the Analysis of Nonlinear Feedback Shift Registers

    Publication Year: 1969, Page(s):824 - 829
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (907 KB)

    Two vector operators θ and γ are introduced. The next-state operator θ allows one to calculate the successors of a set of states {G} from a binary nonlinear feedback shift register. The past-state operator γ allows one to calculate the predecessors of a set of states {G}. Both of these operators, which can be easily programmed on a digital computer, can be used to analyze auton... View full abstract»

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  • Structural Simplification and Decomposition of Asynchronous Sequential Circuits

    Publication Year: 1969, Page(s):830 - 838
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1621 KB)

    In this paper, we extend the partition theory developed by Hartmanis and Stearns for synchronous sequential circuits to asynchronous sequential circuits. A method which utilizes the concept of partition pairs to obtain single transition time asynchronous state assignments with reduced dependence is presented. Parallel and serial decompositions of asynchronous sequential circuits are also considere... View full abstract»

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  • Optimal Synthesis of Arbitrary Switching Functions with Regular Arrays of 2-Input 1-Output Switching Elements

    Publication Year: 1969, Page(s):839 - 856
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3634 KB)

    Most switching functions are not realizable by a single cascade of 2-input 1-output switching elements, even if repeated inputs are allowed. However, arrays of such cascades feeding a single collector cascade of AND or OR cells can be used to synthesize any function. This paper is concerned with optimal array realizations of this form. View full abstract»

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  • On the Lower Bound to the Memory of Finite State Machines

    Publication Year: 1969, Page(s):856 - 861
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1040 KB)

    A finite state machine (FSM) is said to have finite memory μ if μ is the least integer such that yk= f(Xk, Xk-1,... Xk-μ, Yk-1, ... μk-μ) where ykand Xkrepresent the output and input at time k. If no such μ exists, then by convention the memory is said to be infinite. It has been o... View full abstract»

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  • Comment on "Computer-Aided Design: Simulation of Digital Design Logic"

    Publication Year: 1969, Page(s): 862
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    With regard to a recent paper1on computer-aided design, the author and her readers may be interested in some parallel observations and in some unique extensions of capabilities now nearing completion here. View full abstract»

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  • Author's Reply4

    Publication Year: 1969, Page(s): 862
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    I find Mr. McKay's comments very interesting. Time has always been the biggest problem of simulations. However, cost versus time must also be considered. I would like to see a configuration figure of Mr. McKay's system and some form of cost versus time comparisons. Our limited experiences with "dedicated" systems tend to indicate a loss of flexibility and a greater cost versus time comparison. View full abstract»

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  • Remarks on "Comments on 'An Algorithm for Synthesis of Multiple-Output Combinational Logic'"

    Publication Year: 1969, Page(s): 863
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1152 KB)

    In the November 1968 issue of this TRANSACTIONS, the author's paper "Automatic packaging of computer circuitry,"1was referenced in the short note, "Comments on 'An Algorithm for Synthesis of Multiple-Output Combination Logic'," by E. S. Davidson and G. Metze.2This reference might give the impression that the paper gives a procedure for packaging logic on functionally packaged... View full abstract»

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  • Authors' Reply4

    Publication Year: 1969, Page(s):863 - 864
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2432 KB)

    We thank C. H. Haspel for pointing out our error with respect to his packaging procedure. We further basically agree with him as to the trend of logic design toward more logically complex modules. However, we do not share his optimism with regard to the capability of functional decomposition techniques in treating modules of the expected complexity. Rather we envision the evolution of functionally... View full abstract»

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  • R69-26 Further Experimental Data on the Behavior of Programs in a Paging Environment

    Publication Year: 1969, Page(s): 865
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  • R69-27 Demand Paging in Perspective

    Publication Year: 1969, Page(s):865 - 866
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  • R69-28 Dynamic Storage Allocation Systems

    Publication Year: 1969, Page(s): 866
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  • Abstracts of Current Computer Literature

    Publication Year: 1969, Page(s):867 - 884
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  • Information for authors

    Publication Year: 1969, Page(s): 884
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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org