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IEEE Transactions on Computers

Issue 7 • July 1969

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Displaying Results 1 - 22 of 22
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1969, Page(s):c1 - 688
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  • IEEE Computer Group

    Publication Year: 1969, Page(s): c2
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  • Methods Used in an Automatic Logic Design Generator (ALERT)

    Publication Year: 1969, Page(s):593 - 614
    Cited by:  Papers (26)  |  Patents (40)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2944 KB)

    The ALERT system converts preliminary high-level descriptions of computers into logic. The input to ALERT depicts the architecture of a proposed machine in a form of Iverson notation. As output, the architecture is "compiled" into Boolean equations, which may then be converted into standard computer circuits. View full abstract»

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  • A Nonparametric Partitioning Procedure for Pattern Classification

    Publication Year: 1969, Page(s):614 - 624
    Cited by:  Papers (68)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2072 KB)

    A nonparametric procedure is developed for determining a structure for multivariate, multiclass pattern classification. The resultant classifier is in the form of a layered machine which is composed of multithreshold elements. The basic algorithm determines partitions which are parallel hyperplanes orthogonal to the feature coordinate dimensions. Inherent in the procedure is the concept of a trans... View full abstract»

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  • The Characterization and Properties of Cascade Realizable Switching Functions

    Publication Year: 1969, Page(s):624 - 633
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2136 KB)

    This paper is a study of switching functions realizable by a single cascaded switching network composed of two-input, one-output elements where a distinct variable is applied to one input and the other receives the output of the previous element. A special type of Boolean formula called a standard cascade form is introduced with the property that all cascade realizable functions, and only these, c... View full abstract»

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  • Relationships Among Distinct Models and Notions of Equivalence for Stochastic Finite-State Systems

    Publication Year: 1969, Page(s):633 - 641
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1648 KB)

    In an effort to relate various existent schools of thought, this paper describes four models of probabilistic finite-state systems, giving necessary and sufficient conditions for reciprocal describability. An algorithm for the realization (synthesis) of a stochastic sequential machine by a deterministic machine and additive noise is presented. Different definitions of equivalence are listed and re... View full abstract»

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  • Generation of Grey Tones by Computer for Simulation of Visual Information Systems

    Publication Year: 1969, Page(s):642 - 643
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2584 KB)

    It is the evaluation of the subjective fidelity which is of primary importance in any communication system where humans constitute the final information receiver. A method showing how to generate grey-tone increments by computer for displaying simulation results is described. The method is based on the fact that, by over-printing well-defined characters of a commercially available chain printer, g... View full abstract»

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  • A Variable-Length Code for an Incremental Display System

    Publication Year: 1969, Page(s):643 - 644
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1560 KB)

    A compact, simple code for a general-purpose incrementally controlled display system is described. The code consists of three 2-bit incremental bytes, three 4-bit state-control bytes, and a 16-bit data byte which supplies various display parameters or data. View full abstract»

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  • On the Design of Bayesian Storage Allocation Algorithms for Paging and Segmentation

    Publication Year: 1969, Page(s):644 - 651
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1984 KB)

    This short note focuses attention upon techniques for dynamic memory allocation in multiprogrammed systems which employ the addressing mechanisms of paging and segmentation. Here, event indicators and mathematical tools are presented which supply characterizations of the paging and segmentation addressing processes. It is shown that these statistical characterizations form data bases which can be ... View full abstract»

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  • On k-Stable Feedback Shift Registers

    Publication Year: 1969, Page(s):652 - 660
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1840 KB)

    A state graph (SG) is a directed graph with exactly one arc issuing from every vertex of the graph. The degree of an SG is the smallest integer d such that at most d, arcs are entering any vertex of the graph. An SG is said to be k-stable if it contains k≤1 cycles of unit length (loops) and these are the only cycles of the graph. A k-stable SG with mn vertices and degree d is called a (k, m,... View full abstract»

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  • The Design of Shift Register Generators for Finite Sequences

    Publication Year: 1969, Page(s):660 - 662
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    The construction of a shortest feedback shift register which generates a given finite sequence is described for the cases of linear and nonlinear feedback logic. It is shown that the ratio of the number of delay elements required in the linear case to that of the nonlinear case grows without bound for proper choice of sequences. View full abstract»

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  • A Gray Code Counter

    Publication Year: 1969, Page(s):662 - 664
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    A Gray code counter which has an iterative and relatively simple structure is described. The code is shown to be the reflected binary Gray code, implying simple conversion of the count into binary code. View full abstract»

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  • On the Determination of the Maximum Compatibility Classes

    Publication Year: 1969, Page(s): 665
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB)

    In this correspondence an algebraic method of finding the maximum compatibility classes has been described. The two element incompatibles are expressed in the "sum of product" form and a function is obtained which is defined as the incompatibility function. The dual of the incompatibility function is realized, enabling us to obtain the maximum compatibility classes. View full abstract»

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  • Contributors

    Publication Year: 1969, Page(s):666 - 667
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  • R69-16 Satisfaction of Sensitivity Requirements by Threshold Logic Elements

    Publication Year: 1969, Page(s): 668
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  • R69-17 On Finite Automata with a Time-Variant Structure

    Publication Year: 1969, Page(s): 668
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  • R69-18 Multitape One-Way Nonwriting Automata

    Publication Year: 1969, Page(s): 669
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  • R69-19 On the Elimination of Endmarkers

    Publication Year: 1969, Page(s): 669
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  • R69-20 An Analog Card Capacity Correlator as Applied to OCR

    Publication Year: 1969, Page(s):669 - 670
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  • R69-21 Hybrid Assumed Mode Solution of Non-Linear Partial Differential Equations

    Publication Year: 1969, Page(s): 670
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  • Abstracts of Current Computer Literature

    Publication Year: 1969, Page(s):671 - 688
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  • Information for authors

    Publication Year: 1969, Page(s): 688
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org