By Topic

Computers, IEEE Transactions on

Issue 6 • Date June 1969

Filter Results

Displaying Results 1 - 25 of 25
  • IEEE Transactions on Computers - Table of contents

    Page(s): c1 - 592
    Save to Project icon | Request Permissions | PDF file iconPDF (560 KB)  
    Freely Available from IEEE
  • IEEE Computer Group

    Page(s): c2
    Save to Project icon | Request Permissions | PDF file iconPDF (182 KB)  
    Freely Available from IEEE
  • Use of Functional Approximation Methods in the Computer Solution of Initial Value Partial Differential Equation Problems

    Page(s): 499 - 512
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2048 KB)  

    Methods of functional approximation for the computer solution of initial value partial differential equation problems provide a device by which these solutions can be approximated by those of initial value problems in sets of ordinary differential equations. A number of ways to achieve this have been suggested, some of them general, some of them utilizing specific properties of the equations at hand. What all these methods have in common is the fact that the solution u(x, t) of a partial differential equation in space x and time t is approximated by a function u*(a1(t), a2(t), . . ., aN(t)), where the dependence upon x is prescribed. In most applications, u* is linear in the ai(t), i.e., u*= =ai(t)fi(x). The ai(t) satisfy a set of ordinary differential equations obtained as the result of the approximation process. This system of ordinary differential equations is then integrated by classical analog or digital computer methods. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Glass Delay Line Content-Addressed Memory System

    Page(s): 512 - 520
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1464 KB)  

    A glass delay line content-addressed memory system is described which was designed and constructed for use with a general -purpose computing system. A functional description of the system is given along with solutions to the major problems of implementation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The Design of a Highly Parallel Computer Organization

    Page(s): 520 - 529
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1920 KB)  

    The design of a computer organization is presented for general-purpose computing with a very high tolerance of failure while taking advantage of future large-scale integration techniques. A high degree of parallel computations may be executed. The organization distributes processing logic along with memory to form "cells." The architecture and operation of the cells are developed. Design aspects of the cells are presented along with software considerations of the organization. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Path Length Computations on Graph Models of Computations

    Page(s): 530 - 536
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1168 KB)  

    This paper discusses essential difficulties in calculating mean path lengths on a directed graph model of computations. This study was part of a larger study of a priori scheduling of computer programs in a parallel processing environment. Efficient approximations to mean processing time (mean path length) of programs in such an environment are given. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Extending the Definition of Prime Compatibility Classes of States in Incomplete Sequential Machine Reduction

    Page(s): 537 - 540
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (720 KB)  

    A procedure is illustrated to reduce the number of classes of internal states to be considered in the state minimization problem for incompletely specified sequential machines. The procedure leads to an extension of the definition of prime compatibility classes of states. It is based on the updating of the logical closure constraints for prime classes due to previous eliminations of nonprime ones. An additional, more complex elimination mechanism is also presented. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Universal Single Transition Time Asynchronous State Assignments

    Page(s): 541 - 547
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1160 KB)  

    In this paper we consider the problem of deriving upper bounds on the number of state variables required for an n-state universal asynchronous state assignment (i.e., a state assignment which is valid for any n-state asynchronous sequential function). We will consider a special class of state assignments called SST assignments which were first derived by Liu [1] and later extended by Tracey [2]. In these assignments all variables which must change in a given transition are allowed to change simultaneously without critical races. The best universal bound known so far has been developed by Liu and requires 2so-1 state variables, where S0 = [log2n], n being the number of states, and [x] being the least integer > x. We shall show how this bound can be substantially improved. We further show that, by generalizing the state assignment to allow multiple codings for states, the bounds can be still further improved. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of Multicategory Pattern Classifiers with Two-Category Classifier Design Procedures

    Page(s): 548 - 551
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (656 KB)  

    This note derives a relationship between the weights of certain types of R-category linear pattern classifiers and the weights of R two-category linear pattern classifiers. With this relationship R-category classifiers can be designed with computer algorithms for two-category classifier design. Previously proposed R-category classifiers have had to be designed with special R-category classifier design aigorithms. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multiplex Logic Circuits

    Page(s): 552 - 556
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (960 KB)  

    A synthesis procedure must be based upon some cost function or functions. In many systems this cost function is associated with performance. But the usual cost function associated with switching circuits is associated with the cost of realization. Inspection of switching circuits indicates that many switching circuits are not used efficiently and that a measure of component efficiency is the ratio of data rate to component capacity or switching speed. The multiplex logic circuits are designed so that the above efficiency can be improved and as a consequence the number of circuits required can be substantially reduced. Special auxiliary circuits are required. The complexity of these auxiliary circuits is mentioned but not treated. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On the Generation of a Class of Multithreshold Functions

    Page(s): 557 - 559
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (504 KB)  

    Estimates are given for the least common denominator of rational-coefficient realizations of certain classes of multithreshold logic circuits. The result is useful in computer simulation of these functions. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Transformation of Ternary Switching Functions to Completely Symmetric Ternary Switching Functions

    Page(s): 559 - 560
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (320 KB)  

    It is shown that any ternary switching function can be transformed to a completely symmetric ternary switching function in which some of the variables are repeated. The partial symmetry information inherent in a given function plays a key role in this transformation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Some Aids to the Detection of Hazards in Combinational Switching Circuits

    Page(s): 561 - 565
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (728 KB)  

    The detection of hazards in combinational switching networks can be accomplished by Boolean algebra if the independence of component states during transients is taken into account. In this note, several new techniques for carrying out such analysis are introduced. It is also shown that certain ambiguities in previous analysis procedures can lead to incorrect conclusions regarding the presence of dynamic hazards. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Comment on "Canonical Programming of Nonlinear and Time-Varying Differential Equations"

    Page(s): 566
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (176 KB)  

    A recent note by Soudack [1] discusses the application of Levine's method of canonical analog programming [2] to nonlinear and time-varying differential equations. Assuming that only the ai(t) are time-varying, Soudack states that canonical programming cannot be applied to the differential equation E ai(t) piy(t) = E bj(t) piu(t) (1) unless the condition m < n-q (2) is satisfied, where q is "the order of the highest derivative where a nonlinearity occurs, or is the highest derivative multiplied by a time-varying coefficient." View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Error Correction in Batch-Fabricated Memories

    Page(s): 566 - 567
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB)  

    Error correcting codes can be used in memories to produce perfect storage modules from components with some defects. The calculations indicate that the additional complexity of using these codes may be very profitable in increasing the yields of integrated circuit memory arrays. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Modified Twisted-Ring Counter Circuit

    Page(s): 568
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB)  

    In a twisted-ring counter (a feedback shift register in which the next input digit is the complement of the outgoing digit) with three or more stages, the state diagram consists of the desired sequence and other closed sequences composed of unused states. If the counter enters one of the latter, it will not enter the desired sequence. This correspondence points out the minimum modification necessary to ensure that, whatever state the counter is in initially, it will always, in due course, enter the desired sequence. It is shown that the input stage must not be reset unless a group of stages at the opposite end, m in number, are in the 1 state, where m is the smallest integer greater than n/3 and n is the number of stages. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • S-R-T Flip-Flop

    Page(s): 568 - 569
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    Two different definitions for the operating characteristics of the S-R-T flip-flop exist in the literature. These two definitions are discussed, and it is argued that one definition is unnecessarily restrictive while the second is not only more logically correct but leads to more economical circuitry. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Contributors

    Page(s): 570 - 571
    Save to Project icon | Request Permissions | PDF file iconPDF (2317 KB)  
    Freely Available from IEEE
  • R69-13 Perceptrons: An Introduction to Computational Geometry

    Page(s): 572
    Save to Project icon | Request Permissions | PDF file iconPDF (232 KB)  
    Freely Available from IEEE
  • R69-14 Translator Writing Systems

    Page(s): 572 - 573
    Save to Project icon | Request Permissions | PDF file iconPDF (448 KB)  
    Freely Available from IEEE
  • R69-15 Microwave Radar and Electronic Environment Simulator

    Page(s): 573
    Save to Project icon | Request Permissions | PDF file iconPDF (248 KB)  
    Freely Available from IEEE
  • Abstracts of Current Computer Literature

    Page(s): 574 - 592
    Save to Project icon | Request Permissions | PDF file iconPDF (4073 KB)  
    Freely Available from IEEE
  • Blank Page

    Page(s): 592
    Save to Project icon | Request Permissions | PDF file iconPDF (27 KB)  
    Freely Available from IEEE
  • Blank Page

    Page(s): 592
    Save to Project icon | Request Permissions | PDF file iconPDF (27 KB)  
    Freely Available from IEEE
  • Information for authors

    Page(s): 592
    Save to Project icon | Request Permissions | PDF file iconPDF (240 KB)  
    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Albert Y. Zomaya
School of Information Technologies
Building J12
The University of Sydney
Sydney, NSW 2006, Australia
http://www.cs.usyd.edu.au/~zomaya
albert.zomaya@sydney.edu.au