By Topic

Computers, IEEE Transactions on

Issue 3 • Date March 1969

Filter Results

Displaying Results 1 - 25 of 25
  • IEEE Transactions on Computers - Table of contents

    Page(s): c1 - 304
    Save to Project icon | Request Permissions | PDF file iconPDF (573 KB)  
    Freely Available from IEEE
  • IEEE Computer Group

    Page(s): c2
    Save to Project icon | Request Permissions | PDF file iconPDF (260 KB)  
    Freely Available from IEEE
  • Radar Reflectivity Plots—Digital Method

    Page(s): 205 - 211
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1200 KB)  

    An all digital method to produce radar reflectivity plots from analog flight data is presented. The method constitutes a qualitative and operational advance over existing methods. The data are audio-frequency Doppler information extracted from the terrain echo signal of a 13.3-GHz CW scatterometer radar. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Decimal Adder with Signed Digit Arithmetic

    Page(s): 212 - 215
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (736 KB)  

    Addition algorithm, decimal adder with signed digit arithmetic p presented here was designed to establish the following facts: the redundant representation of a decimal digit xi by a 5-bit binary number Xi=3xi leads to a logical design of extreme simplicty; it is possible to form an additional algorithm for the adder so that it can be used to transform numbers written in a conventional decinal form into a signed digit form, and vice versa. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Diagnosis of Single-Gate Failures in Combinational circuits

    Page(s): 216 - 220
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1368 KB)  

    Two procedures are presented for detecting and diagnosing arbitrary single-gate failures in combinational logic circuits. A gate is defined as any multiple-input single-output combinational circuit, and a failure is any detectable transformation of the correct gate function. The testing procedures do not require the construction of a fault table and will locate, to within an equivalence class, the faulty gate and describe its failure. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Calculation of Bayes' Recognition Error for Two Multivariate Gaussian Distributions

    Page(s): 220 - 229
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1928 KB)  

    An algorithm is presented for calculating recognition error when applying pattern vectors to an optimum Bayes' classifier. The pattern vectors are assumed to come from two classes whose populations have Gaussian statistics with unequal covariance matrices and arbitrary a priori probabilities. The quadratic discriminant function associated with a Bayes' classifier is used as a one-dimensional random variable from which the probability of error is calculated, once the distribution of the discriminant function is obtained. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Sequential Boolean Equations

    Page(s): 230 - 240
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2208 KB)  

    The problem of solving sequential Boolean equations is shown to be equivalent to the problem of finding whether there exists a path on a labeled graph for every sequence of labels. Algorithms are given for testing whether a solution exists, and if a solution with a finite delay exists. In case of existence of solutions the algorithms provide them. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Transform for Logic Networks

    Page(s): 241 - 250
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1816 KB)  

    The transform presented in this paper applies to functions which describe logic network behavior. Given a function G defined over a finite domain, it is shown that G(u) = Et F(t)ut for each element u in the domain, where finite-field arithmetic is assumed. Here, function F is the transform of G, and it is shown that F(t) = Eu G(u)(-u)-t for each integer t in a finite set. Both form and development of this transform pair resembles the Fourier transform in harmonic analysis. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Structures of the Affine Families of Switching Functions

    Page(s): 251 - 257
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1432 KB)  

    The equivalence relation that partitions switching functions into affine families leads to a natural graphic representation of the families. From the graphs, it is possible to derive information on the self-symmetries of switching functions and the relative symmetries of functions that are in the same family. A catalog of the structures of the 39 families of four-variable functions appears in the paper. The catalog and, more generally, the theory of affine equivalence are useful tools for the design of logic networks that contain exclusive-OR modules among the set of primitive building blocks. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Loop-Free Threshold Element Structures

    Page(s): 257 - 267
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1512 KB)  

    The paper deals with the problem of "compound" and "cascade threshold" element "synthesis" of an arbitrary Boolean function from the "multithreshold weight threshold vector" (MTWTV). The above synthesis procedure is presented to reveal a unique feature of the multithreshold weight threshold vector, from which several realizations of threshold element nets can be obtained from one of the multithreshold weight threshold vectors. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Calculation of Integrated Circuit Yields

    Page(s): 268
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB)  

    This note describes the simple calculation required to obtain circuit yields from component yields for integrated circuits. A graph is presented to illustrate the high component yields required for MSI and LSI technology. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Digital Comparator for Use with Computer Displays

    Page(s): 269 - 270
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (504 KB)  

    A digital comparator has been attached to a PDP-4/340 display terminal. This comparator is used to detect the presence of the CRT beam within a specified portion of the display screen. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On (d, k, μ) Graphs

    Page(s): 270 - 272
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (704 KB)  

    A (d, k, μ graph is defined as a graph in which every vertex has degree at most d, and every pair of vertices are joined by μ edge-disjoint paths, each of length at most k. The order of a graph is the number of vertices it contains. N(d, k, μ) is the number that is the largest of all the orders of ( d, k, μ) graphs. Elspas has investigated , k, pμ graphs when k= 2 and when k = .μ In this paper, (d, k, μ) graphs for d = μ are constructed, yielding lower bounds on N(d, k, d). Further, for d= k = μ = 3, N( d, k, μ) is determined and the graphs attaining this order are characterized. ( d, k, μ) graphs are potentially useful in determining how propagation delay, terminal packing factors, and possible blocking conditions may constrain a modeled digital system. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Mixed Memory Type Realizations of Sequential Machines

    Page(s): 272 - 277
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1488 KB)  

    In this note, we examine the problem of finding good state assignments when mixed memory type realizations (i.e., including mixtures of delay and trigger flip-flop memories) are permitted. Specifically, we describe situations that take advantage of this extra degree of design freedom, and we indicate how to modify two existing algorithms to determine such mixed realizations systematically. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Full text access may be available. Click article title to sign in or learn about subscription options.
  • Identification of Disjunctively Decomposable Logic Functions Employing a Karnaugh Map

    Page(s): 277 - 279
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (784 KB)  

    This crrespondence is concerned with the develop-ment of a simple set of rules used to determine disjunctively decomposable logic functions by means of a single Karnaugh map. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Attenuationless Voltage or Current Propagation on a Line with Ohmic Losses

    Page(s): 280 - 281
    Save to Project icon | Request Permissions | PDF file iconPDF (1504 KB)  
    Freely Available from IEEE
  • Comment on "A Variable Counter Design Technique"

    Page(s): 281
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1312 KB)  

    In Renschler's short note1 the variable counter (Fig. 3) and divide-by-N counter (Fig. 4) could be simplified in terms of the number of logic elements involved and the total cost to implement. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Author's Reply2

    Page(s): 281
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1312 KB)  

    The suggested simplifications of the system designs (Figs. 3 and 4) offered by Davis in his above comment are quite simple, straight-forward, and certainly valid, as one must consider these economical factors when a system of this type is designed. However, I think he has missed the point of the whole short note, at least as it was intended. It attempted not to offer a minimum-cost fully optimized system, but merely to discuss the concept of programmable clocked counters in general terms, as I thought the subject was very interesting, yet had failed to find it documented anywhere in the literature echnical journals or trade magazines). View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Another Comment on "A Variable Counter Design Technique"

    Page(s): 281 - 282
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2424 KB)  

    The divide-by-N counter outlined in Fig. 4 of Renschlerl appears to be severely overcomplicated, due, I suspect, to the author's having devised the decimal-BCD converter of Fig. 2 for a divide-by-N down counter, and then adding gating circuitry in order to use this converter in an up-counter. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Author's reply2

    Page(s): 282 - 284
    Save to Project icon | Request Permissions | PDF file iconPDF (3989 KB)  
    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Abstracts of Current Computer Literature

    Page(s): 285 - 302
    Save to Project icon | Request Permissions | PDF file iconPDF (5104 KB)  
    Freely Available from IEEE
  • R69-5 The Statistics of Discrete-Event Simulation

    Page(s): 303
    Save to Project icon | Request Permissions | PDF file iconPDF (216 KB)  
    Freely Available from IEEE
  • R69-6 Trajectory Optimization by a Direct Descent Process

    Page(s): 303 - 304
    Save to Project icon | Request Permissions | PDF file iconPDF (304 KB)  
    Freely Available from IEEE
  • Information for authors

    Page(s): 304
    Save to Project icon | Request Permissions | PDF file iconPDF (250 KB)  
    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Albert Y. Zomaya
School of Information Technologies
Building J12
The University of Sydney
Sydney, NSW 2006, Australia
http://www.cs.usyd.edu.au/~zomaya
albert.zomaya@sydney.edu.au