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IEEE Transactions on Computers

Issue 1 • Date Jan. 1969

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Displaying Results 1 - 22 of 22
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1969, Page(s): c1
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  • IEEE Computer Group

    Publication Year: 1969, Page(s): c2
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  • Computer-Aided Design: Simulation of Digital Design Logic

    Publication Year: 1969, Page(s):1 - 10
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1424 KB)

    In the ever-increasing trend to relieve man of time consuming menial tasks via automation, the digital logic designer's tasks have come under study. Various phases of this work are now being performed by computers. One of these phases, simulation of digital designs, is the topic of this paper. View full abstract»

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  • Logic Design Automation of Fan-In Limited NAND Networks

    Publication Year: 1969, Page(s):11 - 22
    Cited by:  Papers (26)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2216 KB)

    Factoring techniques are incorporated in computer-oriented algorithms for the synthesis of fan-in limited NAND switching networks. Tree networks with reduced gate count or levels of logic are sought. While example FORTRAN programs emphasize computer execution of the algorithms, they are also efficient for hand execution. View full abstract»

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  • A Methodical Approach to Analyzing and Synthesizing a Self-Repairing Computer

    Publication Year: 1969, Page(s):22 - 42
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4312 KB)

    The literature on computer reliability is replete with very convincing arguments for the need and the use of self-repair techniques, as a viable approach to significantly enhancing the reliability of both maintainable and nonmaintainable computers. However, it would seem that no comprehensive and coherent program for the development and optimal employment of such techniques exists. This means that... View full abstract»

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  • High-Speed DC Coupled Digit Detector

    Publication Year: 1969, Page(s):43 - 47
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1992 KB)

    The requirements, design, and performance of an integrable dc coupled digit detector array for high-speed memory systems such as the plated wire is described. The array consists of 12 detectors on 100-mil centers, on a tantalum film glass substrate using beam-lead monolithic chips. There are 218 resistors and 144 beam lead transistors formed or bonded with an area of 0.8 × 1.2 inch. Ninety-si... View full abstract»

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  • Module Clustering to Minimize Delay in Digital Networks

    Publication Year: 1969, Page(s):47 - 57
    Cited by:  Papers (54)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3008 KB)

    An important aspect of the packaging of digital networks is the allocation of logic gates to modules such that a predetermined objective function is minimized. In order to develop techniques for this partitioning of a logic network we have considered the following problem: Given an acyclic combinational network composed of various primitive blocks such as NOR gates, assume that a maximum of M gate... View full abstract»

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  • Computer Reduction of Two-Level, Multiple-Output Switching Circuits

    Publication Year: 1969, Page(s):58 - 63
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (992 KB)

    An algorithm which reduces the number of gates and connections (diodes) in two-level, multiple-output combinational logic networks is presented and compared with conventional minimization procedures. View full abstract»

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  • A Simplified Analysis of Processor "Look-Ahead" and Simultaneous Operation of a Multi-Module Main Memory

    Publication Year: 1969, Page(s):64 - 71
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1600 KB)

    This paper focuses attention upon the design of a processor and memory system which is structured to achieve a satisfactory balance of processor speed and memory speed when both the processor and input–output controller are simultaneously competing for memory service. A mathematical model is developed to investigate the degree to which the processor is capable of overlapping memory reference... View full abstract»

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  • Binary Multiplication with Overlapped Addition Cycles

    Publication Year: 1969, Page(s):71 - 74
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (968 KB)

    With a suitable adder organization it is possible to overlap the adder operation during a binary multiplication and significantly decrease the overall multiplication time. The method is explained and a prototype multiplier described. The new technique provides a very economical method of obtaining a reasonably fast multiplier. View full abstract»

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  • Incrementing a Bit-Reversed Integer

    Publication Year: 1969, Page(s): 74
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    A fast method of generating bit-reversed addresses for the fast Fourier transform is described. View full abstract»

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  • Subtraction by Minuend Complementation

    Publication Year: 1969, Page(s):74 - 76
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (872 KB)

    In performing the operation of subtraction in additive systems, a popular practice is to complement the subtrahend and add. A second method of performing subtraction, which seems to have been overlooked, is to complement the minuend, add it to the subtrahend, and complement the result. In many cases, this second method is more awkward; however, in two instances it seems to be worthy of considerati... View full abstract»

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  • Note on a Class of Statistical Recognition Functions

    Publication Year: 1969, Page(s):76 - 79
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (792 KB)

    Statistical recognition procedures can be derived from the functional form of underlying probability distributions. Successive approximation to the probability function leads to a class of recognition procedures. In this note we give a hierarchical method of designing recognition functions which satisfy both the least-square error property and a minimum decision error rate property, although our d... View full abstract»

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  • Comment on "Generalized Parallel Redundancy in Digital Computers"

    Publication Year: 1969, Page(s): 80
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    In his recent short note on redundancy,1Deo overlooks an important failure-free condition that takes into account the cancellation of votes by two modules failing in opposing states. View full abstract»

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  • Author's Reply3

    Publication Year: 1969, Page(s): 80
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    In general, when a logical element fails it can fail not only at true or false levels but at any one of infinitely many different voltage levels. Thus, strictly speaking, one should talk of probability density function, rather than discrete probabilities. When considering the simultaneous failures of several modules one has to consider the joint probability density function. View full abstract»

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  • Comment on "A Variable Counter Design Technique"

    Publication Year: 1969, Page(s): 80
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  • Contributors

    Publication Year: 1969, Page(s):81 - 82
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  • R69-1 Transport Time-Delay Simulation for Transmission Line Representation

    Publication Year: 1969, Page(s): 83
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  • R69-2 The Synthesis and Processing of Signals with Discontinuities in the Time Domain

    Publication Year: 1969, Page(s):83 - 84
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  • Abstracts of Current Computer Literature

    Publication Year: 1969, Page(s):85 - 104
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  • Information for authors

    Publication Year: 1969, Page(s): 104
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  • Blank Page

    Publication Year: 1969, Page(s): 104
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org