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Computers, IEEE Transactions on

Issue 1 • Date Jan 1992

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Displaying Results 1 - 14 of 14
  • An efficient implementation of Boolean functions as self-timed circuits

    Page(s): 2 - 11
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (784 KB)  

    The authors propose a general synthesis method for efficiently implementing any family of Boolean functions over a set of variables, as a self-timed logic module. Interval temporal logic is used to express the constraints that are formulated for the self-timed logic module. A method is provided for proving the correct behavior of the designed circuit, by showing that it obeys all the functional constraints. The resulting circuit is compared with alternative proposed self-timed methodologies. This approach is shown to require less gates than other methods. The proposed method is appropriate for automatic synthesis of self-timed systems. A formal proof of correctness is provided View full abstract»

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  • Performance analysis of multistage interconnection network configurations and operations

    Page(s): 18 - 27
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    A performance evaluation using both analytical and simulation models, of circuit-switching multistage interconnection networks in aspects of configurations and operations is presented. Two configurations of the networks, single and dual, are evaluated. Network operations considered include conflict resolution strategies and communication strategies. Two different conflict resolution strategies, drop and hold, are analyzed. New analyses using Markov chains, are given, and are verified by simulation results. In the single-network configuration, it is shown that the drop strategy is better than the hold strategy for randomly distributed traffic. In the dual network configuration, five different communication strategies are investigated, and the optimum performance level is shown to be dependent on the length of the data transfer time View full abstract»

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  • Implementing sequential machines as self-timed circuits

    Page(s): 12 - 17
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    A self-timed finite state machine (FSM) is described. It is based on a formally proven, efficient implementation of self-timed combinational logic and a self-timed master-slave register. Temporal behavioral constraints are formalized, and the system is shown to abide by them. The synthesis method is algorithmic and serves as an automatic compiler of self-timed FSMs. The specification of the FSM is given by a state table, similar to that of synchronous machines. The circuit operates according to a sequence of events that replaces the role of the central clock in the synchronous FSM. The inputs and outputs of the circuit are double-rail (or ternary) and the circuit produces a completion signal. The method is compared with other approaches View full abstract»

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  • P-functions-ternary logic functions capable of correcting input failures and suitable for treating ambiguities

    Page(s): 28 - 35
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (660 KB)  

    The authors consider a new class of special ternary logic functions: the P-functions capable of correcting input failures, based on the regular ternary logic. There are three major results. First, the P-functions are a special subset of the regular functions with no information loss. Second a ternary logic function defined by the all-prime-implicant disjoint of any Boolean connective is a P-function. Third, a P-function may be identified from the irredundant disjunctive form. The relationship between P-functions and other meaningful ternary logic functions is discussed View full abstract»

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  • String editing on a one-way linear array of finite-state machines

    Page(s): 112 - 118
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    The authors give an efficient parallel algorithm for the string edit problem. The model of computation is a one-way linear array of identical finite-state machines (nodes). The data movement in the array is one-way, from left to right. For inputs of length n, the array uses n nodes. The algorithm can produce the actual minimum-cost edit sequence in linear time. The previous parallel algorithm for this problem runs in O(n) time on a one-way two-dimensional array of finite-state machines using n 2 nodes. The best serial (RAM) algorithm for the problem takes O(n2/log n) time and space. Applications to other problems such as the longest common subsequence and approximate pattern matching are discussed View full abstract»

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  • A circular binary search

    Page(s): 109 - 112
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    In a standard binary search, the binary representation of the index of an element in an ordered linear array is recovered serially bit by bit. For an array of N elements, the index of an element is recovered, in principle, by assigning to each element one value out of log2 N possibilities. It is shown here that by arranging 2n-1 elements in a circular array, the bits of the binary representation of the index of an element are all recovered simultaneously based n assigning to each element one value out of two possibilities. The main theoretical result shows that the parity of an integer X is trivially recovered from the parity of the Hamming weight of the binary representation of X, X+1, X +2, and X+3, whereas, on the other hand, the parity of the Hamming weight of the binary representation of an integer is consistent with modular arithmetic considerations View full abstract»

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  • A systolic algorithm for the k-nearest neighbors problem

    Page(s): 103 - 108
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    The authors present a systolic algorithm and its variations for the k-nearest neighbors problem (kNNP). Multiple-shot queries with different ranges (k values) can be served in a pipelined fashion. A partitioning scheme is developed to handle large size problems. Performance of the algorithm is analyzed. Formulas for the optimal array size in terms of computation time and area-time-time product (ATT) are derived. The algorithm can solve a multiple-shot k NNP in N+2√N×K systolic steps using √N×K processing elements, where N is the problem size (i.e. the number of points), and K is the sum of all k-values View full abstract»

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  • Design and evaluation of the rollback chip: special purpose hardware for Time Warp

    Page(s): 68 - 82
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    Existing approaches to implement state saving are not appropriate for large Time Warp programs. The authors propose a component called the rollback chip (RBC) that efficiently implements state saving. Such a component could be used in a programmable, special purpose parallel discrete event simulation engine based on Time Warp. The algorithms implemented by the rollback chip are described, as well as mechanisms that allow efficient implementation. Results of simulation studies are presented that show that the rollback chip can virtually eliminate the state saving and rollback overheads that plague current software implementations of Time Warp View full abstract»

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  • Statistical resistance to detection [digital circuits testing]

    Page(s): 123 - 126
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    Discusses the problem of estimating the sum of the detection probabilities of the yet unobserved faults during a random pattern test of a given digital circuit. The authors describe a statistical method for this purpose. The method requires keeping track of each fault until it is detected for the second time, and thus the simulation cost is about twice the cost of a similar simulation which abandons faults after their first detect. The benefits of having an estimate of the sum of these detection probabilities are twofold: (1) it provides a good stopping rule whenever 100% fault coverage is infeasible (which is often the case), and (2) it provides an estimate of the required effort to detect the next fault. The results of tests performed on some circuits are presented View full abstract»

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  • Test scheduling in high performance VLSI system implementations

    Page(s): 52 - 67
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    The authors provide tools for exploring the inherent parallelism introduced by design for testability (DFT) and built-in self-test (BIST) techniques in order to reduce test length. Since the potential for parallel test execution is most apparent at the organization level and DFT and BIST hardware is also often added at that level, the organization level is used as a foundation for the work. A broader modeling foundation that encompasses both dimensions, space and time, of test parallelism is introduced. A set of simple schedulability criteria for concurrent issuing of tests is developed. Effective suboptimum heuristic-based algorithms for scheduling tests on general-purpose high-performance VLSI system implementation are presented. The scheduling algorithms have been implemented and performance results are presented View full abstract»

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  • Constructing parallel paths between two subcubes

    Page(s): 118 - 123
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    The authors consider a hypercube system that runs more than one job at a time, with each job allocated a subcube. They discuss the problem of migrating (relocating) a job from one subcube to another, assuming a circuit-switching hypercube network. An algorithm is presented for constructing parallel circuits between two subcubes so that the tasks of a job can be migrated simultaneously. It is shown that no matter how fragmented the hypercube is, one can always construct parallel paths between two given subcubes. Furthermore, one can always minimize the maximum length of the constructed circuits. A solution that minimizes the maximum length of the circuits will also minimize the total length. The circuits are mutually edge-disjoint and do not use any edge that has been used by other jobs. The time complexity of the algorithm is O(n2m), where n is the dimension of the hypercube system and m is the number of jobs already in the system View full abstract»

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  • Sorting with linear speedup on a pipelined hypercube

    Page(s): 97 - 103
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    The authors formally define a distributed-memory parallel architecture called the pipelined hypercube. A coarse-grained parallel sorting algorithm that can be mapped efficiently on such an architecture is also presented. The pipelined hypercube has a more powerful communication mechanism than the traditional binary code architecture, in that it permits communication of blocks of data between processing elements (PEs) to be performed in a pipelined manner. Certain data communication problems which would probably be serialized on the binary code architecture, can be performed optimally on the pipelined hypercube. The sorting algorithm can be mapped efficiently onto a pipelined hypercube of P PEs. It sorts N data items, initially distributed among the PEs, in time O((N log N/P)+log2 P), thereby achieving linear speedup when P is O(N/log N) View full abstract»

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  • Reconfiguration strategies for VLSI processor arrays and trees using a modified Diogenes approach

    Page(s): 83 - 96
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    The authors deal with reconfiguration of a rectangular array of processors arranged as an N×N mesh, and a complete binary tree of N processors. They present new reconfiguration techniques that are modifications of the Diogenes approach proposed earlier by A.L. Rosenberg et al. (1983). These techniques reduce the overheads incurred in the earlier Diogenes schemes. Some of the previous approaches to the problem are summarized. Two schemes are presented for reconfiguring rectangular arrays and a scheme for reconfiguring trees. For the analysis of the different schemes presented, it is assumed that a processor has a square layout. These schemes are analyzed and their performance results are presented View full abstract»

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  • A unified framework for simulating Markovian models of highly dependable systems

    Page(s): 36 - 51
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    The authors present a unified framework for simulating Markovian models of highly dependable systems. It is shown that a variance reduction technique called importance sampling can be used to speed up the simulation by many orders of magnitude over standard simulation. This technique can be combined very effectively with regenerative simulation to estimate measures such as steady-state availability and mean time to failure. Moveover, it can be combined with conditional Monte Carlo methods to quickly estimate transient measures such as reliability, expected interval availability, and the distribution of interval availability. The authors show the effectiveness of these methods by using them to simulate large dependability models. They discuss how these methods can be implemented in a software package to compute both transient and steady-state measures simultaneously from the same sample run View full abstract»

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