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Semiconductor Manufacturing, IEEE Transactions on

Issue 3 • Date Aug. 2006

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  • Table of contents

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  • IEEE Transactions on Semiconductor Manufacturing publication information

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  • Optimization of photomask design for reducing aberration-induced placement error

    Page(s): 277 - 285
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (639 KB) |  | HTML iconHTML  

    In semiconductor manufacturing, the accurate placement of circuit components ensures the proper functioning of microelectronic circuits. This is often subject to photolithography, an optical technique that transfers circuit patterns from photomasks to silicon wafers. Sources of placement error include aberration and misalignment between different levels, and we focus on the former. Aberration is an optical phenomenon that often degrades imaging system performance. Since aberration differs from one imaging system to another, a photomask design that minimizes the aberration-induced placement error is desired. In this paper, we discuss the optimization process of a general one-dimensional mask pattern under a general illumination condition. The constraint is a known population mean of the root mean square aberrations for the imaging systems under consideration. To apply the theory, we search for the optimal parameters for two common mask designs: alternating phase-shifting masks (PSMs) and attenuated PSMs. The theoretical results are compared with those from a Monte Carlo analysis on a large set of imaging systems. These results are indicative to mask manufacturers and circuit designers of increasing manufacturability of circuits View full abstract»

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  • Simulations for the effect of chamber geometry on oxygen plasma characteristics for very large plasma sources

    Page(s): 286 - 291
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1148 KB) |  | HTML iconHTML  

    Using an oxygen discharge model based on diffusion equations, we numerically investigate the effect of chamber geometry on plasma density profiles, especially for very large rectangular high-density plasma chambers. The calculation results show that uniformity of the ion and O-atom density profiles seriously deteriorates when the chamber length increases up to 2 m. We discuss the dependence of the plasma density profiles on the chamber geometry in terms of the relationship between particle generation in the volume and loss at the wall surface. The simulation results indicate that the surface loss at the top and bottom chamber walls dominates the loss at the side walls. The density profiles, therefore, vary, depending on the chamber length even at the same aspect ratio. The simulation results also predict that the uniformity of the density profiles could be significantly improved over the very large area if the plasma were properly confined by using magnetic multipole fields, along with choosing suitable wall materials that influence the particle loss at the surface View full abstract»

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  • Transient thermal analysis of sapphire wafers subjected to thermal shocks

    Page(s): 292 - 297
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (310 KB) |  | HTML iconHTML  

    Rapid heating and cooling are commonly encountered events in integrated circuit processing, which produce thermal shocks and consequent thermal stresses in wafers. The present paper studies the heat transfer in sapphire wafers during a thermal shock as well as the dependence of the wafer temperature on various process parameters. A three-dimensional finite-element model of a single sapphire wafer was developed to analyze the transient heat conduction in conjunction with the heat radiation and heat convection on the wafer surfaces. A silicon wafer was also investigated, for comparison. It was found that the rapid thermal loading leads to a parabolic radial temperature distribution, which induces thermal stresses even if the wafer is not mechanically restrained. The study predicted that for sapphire wafers the maximum furnace temperature of 800 degC should be held for two hours in order to get a uniform temperature throughout the wafer View full abstract»

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  • Just-in-time adaptive disturbance estimation for run-to-run control of semiconductor processes

    Page(s): 298 - 315
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (691 KB) |  | HTML iconHTML  

    Run-to-run control is the term used for the application of discrete parts manufacturing control as practiced in the semiconductor industry. This paper presents a new algorithm for use in run-to-run control that has been designed to address some of the challenging issues unique to batch-type manufacturing. Just-in-time adaptive disturbance estimation (JADE) uses recursive weighted least squares parameter estimation to identify the contributions to variation that are dependent upon manufacturing context. The strengths and weaknesses of the JADE algorithm are demonstrated in a series of test cases developed to separate the various disturbances and processing issues a control system would be expected to encounter View full abstract»

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  • Temperature and Substrate Effects in Monolithic RF Inductors on Silicon With 6- \mu\hbox {m} -Thick Top Metal for RFIC Applications

    Page(s): 316 - 330
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1408 KB) |  | HTML iconHTML  

    Comprehensive analyses of the effects of temperature (from -50degC to 200 degC), silicon substrate thickness, and proton implantation postprocess on the performances of a set of planar spiral inductors with 6-mum-thick top metal are demonstrated. Quality-factor (Q-factor) and power gain (GA) decrease with increasing temperatures but show a reverse behavior within a higher frequency range. Stability-factor (K-factor) and noise figure (NF) increase with increasing temperatures but show a reverse behavior within a higher frequency range. The reverse frequencies fR, which correspond to the zero temperature coefficient of GA, K-factor, and NF, are almost the same. In addition, both the silicon substrate thinning and proton implantation are verified to be effective in improving the Q-factor and NF performances of inductors on silicon. The present analyses enable RF engineers to understand more deeply the Q-factor and NF behavior of inductors fabricated on a thin silicon substrate (20 mum) and hence are helpful for them to design high-performance fully on-chip low-noise-amplifiers and other RF integrated circuits View full abstract»

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  • Low-K/Cu CMOS-based SoC technology with 115-GHz f/sub T/, 100-GHz f/sub max/, low noise 80-nm RF CMOS, high-Q MiM capacitor, and spiral Cu inductor

    Page(s): 331 - 338
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    Logic CMOS-based RF technology is introduced for a 10-Gb transceiver in which active and passive RF devices have been realized in a single chip. RF nMOS of 115-GHz fT, 100-GHz fmax, and sub-1.0-dB NFmin at 10 GHz have been fabricated by aggressive device scaling and layout optimization. High-Q MiM capacitor and spiral Cu inductors have been successfully implemented in the same chip by 0.13-mum low-K/Cu back end of integration line technology. Core 1.0 V MOS and/or junction varactors for VCO at 10 GHz are offerings free of extra cost and realized by the elaborated layout View full abstract»

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  • Multicluster tools scheduling: an integrated event graph and network model approach

    Page(s): 339 - 351
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    Steady-state throughput and scheduling of a multicluster tool become complex as the number of modules and clusters grows. We propose a new methodology integrating event graph and network models to study the scheduling and throughput of multicluster tools. A symbolic decision-move-done graph modeling is developed to simplify discrete-event dynamics for the multicluster tool. This event graph is further used for searching feasible action sequences of the cluster tool. By representing sequences with networks, an extended critical path method is applied to calculate the corresponding cycle time. Grouping methods that are based on network are also introduced to reduce the searching complexity. Compared with optimization-based scheduling approaches, the proposed methodology can directly capture the cyclic characteristic of cluster tool schedules and be applied to analyze the impact of process and wafer flow variations on cycle time and robot schedules. We have successfully applied this new methodology to dozens of cluster tools at Intel Corporation. A chemical-mechanical planarization polisher is employed as an example to illustrate and validate the proposed methodology View full abstract»

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  • The development of the complete X-factor contribution measurement for improving cycle time and cycle time variability

    Page(s): 352 - 362
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (937 KB) |  | HTML iconHTML  

    Reducing variability in a manufacturing process lowers system cycle times. Semiconductor manufacturing is a variable process due in part to product mix, reentry lot flows, batching, and machine breakdowns. This paper examines the issue of identifying machines that introduce variability into the system and constrain the system capacity. We develop a new X-factor contribution measurement, the complete X factor, that considers processing time variability and lot arrival variability among the constraining qualities of the machine groups. This new measure uses machine level data to indicate the normalized system cycle time which has typically been estimated by the ratio of the entire process time and the raw processing time at the end of production. With this measure it becomes possible for factory floor managers to identify a capacity constraining machine and its impact on the overall cycle time directly. We first qualitatively present the justification of the complete X factor for representing the normalized cycle time using queuing theory. Then, the complete X-factor measure was tested on a full-scale simulation model to demonstrate its accuracy for detecting capacity constraining machine groups and for representing normalized cycle time. We also explore the propagation of variability and the effect a highly variable machine group has on product cycle time and cycle time variability in relation to process routing. In a full-scale model machines identified by the complete X-factor contribution measure (CXC) measure lowered cycle time as effectively as highly utilized machines by adding capacity or streamlining breakdowns but had a more prominent effect on lowering cycle time variability. After a brief study on the propagation of variability, the CXC measure identified a lower utilized backend process that reduced cycle time and cycle time variability of the system View full abstract»

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  • 2006 IEEE International Electron Devices Meeting

    Page(s): 363
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  • IEEE International Soild-State Circuits Conference (ISSCC 2007)

    Page(s): 364
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  • 22nd IEEE Non-Volatile Semiconductor Memory Workshop 2007

    Page(s): 365
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  • EDS archival collection on DVD

    Page(s): 366
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  • Join EDS and get online access [advertisement]

    Page(s): 367
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  • Explore IEL IEEE's most comprehensive resource [advertisement]

    Page(s): 368
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  • IEEE Transactions on Semiconductor Manufacturing Information for authors

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  • Blank page [back cover]

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Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

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Meet Our Editors

Editor-in-Chief

Anthony Muscat
Department of Chemical and Environmental Engineering
Harshbarger Bldg., Room 134
1133 E. James Rogers Way
University of Arizona
Tucson, AZ  85721