IEEE Transactions on Computers

Issue 9 • Sept. 2006

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Displaying Results 1 - 21 of 21
  • [Front cover]

    Publication Year: 2006, Page(s): c1
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  • [Inside front cover]

    Publication Year: 2006, Page(s): c2
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  • Guest Editors' Introduction: Special Section on Fault Diagnosis and Tolerance in Cryptography

    Publication Year: 2006, Page(s):1073 - 1074
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  • A Fault Attack on Pairing-Based Cryptography

    Publication Year: 2006, Page(s):1075 - 1080
    Cited by:  Papers (30)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (137 KB) | HTML iconHTML

    Current fault attacks against public key cryptography focus on traditional schemes, such as RSA and ECC, and, to a lesser extent, on primitives such as XTR. However, bilinear maps, or pairings, have presented theorists with a new and increasingly popular way of constructing cryptographic protocols. Most notably, this has resulted in efficient methods for identity based encryption (IBE). Since iden... View full abstract»

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  • Combining Crypto with Biometrics Effectively

    Publication Year: 2006, Page(s):1081 - 1088
    Cited by:  Papers (211)  |  Patents (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1121 KB) | HTML iconHTML

    We propose the first practical and secure way to integrate the iris biometric into cryptographic applications. A repeatable binary string, which we call a biometric key, is generated reliably from genuine iris codes. A well-known difficulty has been how to cope with the 10 to 20 percent of error bits within an iris code and derive an error-free key. To solve this problem, we carefully studied the ... View full abstract»

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  • Fault Detection Architectures for Field Multiplication Using Polynomial Bases

    Publication Year: 2006, Page(s):1089 - 1103
    Cited by:  Papers (42)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3334 KB) | HTML iconHTML

    In many cryptographic schemes, the most time consuming basic arithmetic operation is the finite field multiplication and its hardware implementation for bit parallel operation may require millions of logic gates. Some of these gates may become faulty in the field due to natural causes or malicious attacks, which may lead to the generation of erroneous outputs by the multiplier. In this paper, we p... View full abstract»

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  • Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic

    Publication Year: 2006, Page(s):1104 - 1115
    Cited by:  Papers (35)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2461 KB) | HTML iconHTML

    This paper presents hardening techniques against fault attacks and the practical evaluation of their efficiency. The circuit technology investigated to improve the resistance against fault attacks is asynchronous logic. Specific properties of asynchronous circuits make them inherently resistant against a large class of faults. An analysis of their behavior in the presence of faults shows that they... View full abstract»

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  • An RSA Implementation Resistant to Fault Attacks and to Simple Power Analysis

    Publication Year: 2006, Page(s):1116 - 1120
    Cited by:  Papers (48)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (575 KB) | HTML iconHTML

    Nowadays, side channel attacks allow an attacker to recover secrets stored in embedded devices more efficiently than any other kind of attack. Among the former, fault attacks (FA) and single power analysis (SPA) are probably the most effective: when applied to straightforward implementations of the RSA cryptosystem, only one execution of the algorithm is required to recover the secret key. Over re... View full abstract»

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  • Frame-Based Proportional Round-Robin

    Publication Year: 2006, Page(s):1121 - 1129
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1360 KB) | HTML iconHTML

    All known real-time proportional fair scheduling mechanisms either have high scheduling overheads (O(lg n) per time-slot) or do not efficiently handle dynamic task sets. This paper presents frame-based proportional round-robin (FBPRR), a real-time fair scheduler providing high and bounded proportional fairness accuracy and O(1) scheduling overhead with the ability to efficiently handle a set of dy... View full abstract»

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  • Dual-Homing Based Scalable Partia Multicast Protection

    Publication Year: 2006, Page(s):1130 - 1141
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1697 KB) | HTML iconHTML

    In this paper, we propose a scalable multicast protection scheme based on a dual-homing architecture where each destination host is connected to two edge routers. Under such an architecture, there are two paths from the source of a multicast session to each destination host, which provides a certain level of protection for the data traffic from the source to the destination host. The protection le... View full abstract»

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  • Throttling-Based Resource Management in High Performance Multithreaded Architectures

    Publication Year: 2006, Page(s):1142 - 1152
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2536 KB) | HTML iconHTML

    Up to now, the power problems which could be caused by the huge amount of hardware resources present in modern systems have not been a primary concern. More recently, however, power consumption has begun limiting the number of resources which can be safely integrated into a single package, lest the heat dissipation exceed physical limits (before actual package meltdown). At the same time, new arch... View full abstract»

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  • Early Register Deallocation Mechanisms Using Checkpointed Register Files

    Publication Year: 2006, Page(s):1153 - 1166
    Cited by:  Papers (9)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6398 KB) | HTML iconHTML

    Modern superscalar microprocessors need sizable register files to support a large number of in-flight instructions for exploiting instruction level parallelism (ILP). An alternative to building large register files is to use a smaller number of registers, but manage them more effectively. More efficient management of registers can also result in higher performance if the reduction of the register ... View full abstract»

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  • Arithmetic Operations in Finite Fields of Medium Prime Characteristic Using the Lagrange Representation

    Publication Year: 2006, Page(s):1167 - 1177
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB) | HTML iconHTML

    In this paper, we propose a complete set of algorithms for the arithmetic operations in finite fields of prime medium characteristic. The elements of the fields IFpk are represented using the newly defined Lagrange representation, where polynomials are expressed using their values at sufficiently many points. Our multiplication algorithm, which uses a Montgomery approach, can be impleme... View full abstract»

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  • On Optimal Deadlock Detection Scheduling

    Publication Year: 2006, Page(s):1178 - 1187
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (830 KB) | HTML iconHTML

    Deadlock detection scheduling is an important, yet often overlooked problem that can significantly affect the overall performance of deadlock handling. Excessive initiation of deadlock detection increases overall message usage, resulting in degraded system performance in the absence of deadlocks, while insufficient initiation of deadlock detection increases the deadlock persistence time, resulting... View full abstract»

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  • Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs

    Publication Year: 2006, Page(s):1188 - 1201
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1941 KB) | HTML iconHTML

    A Taylor expansion diagram (TED) is a compact, word-level, canonical representation for data flow computations that can be expressed as multivariate polynomials. TEDs are based on a decomposition scheme using Taylor series expansion that allows one to model word-level signals as algebraic symbols. This power of abstraction, combined with the canonicity and compactness of TED, makes it applicable t... View full abstract»

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  • Relationship between GF(2^m) Montgomery and Shifted Polynomial Basis Multiplication Algorithms

    Publication Year: 2006, Page(s):1202 - 1206
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (219 KB) | HTML iconHTML

    Applying the matrix-vector product idea of the Mastrovito multiplier to the GF(2m) Montgomery multiplication algorithm, we present a new parallel multiplier for irreducible trinomials. This multiplier and the corresponding shifted polynomial basis (SPB) multiplier have the same circuit structure for the same set of parameters. Furthermore, by establishing isomorphisms between the Montgo... View full abstract»

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  • Improvement to Montgomery Modular Inverse Algorithm

    Publication Year: 2006, Page(s):1207 - 1210
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (363 KB) | HTML iconHTML

    After a comprehensive study on the Montgomery modular inverse algorithm and its revised versions, two modified high radix algorithms are proposed which utilize higher radix to reduce iterations needed without increasing complexity much, thereby accelerating the process. The radix-4 algorithm can reduce the average number of iterations from 1.4 n to 0.82 n and a software experiment shows the speedu... View full abstract»

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  • Efficient Bit-Parallel Multiplier for Irreducible Pentanomials Using a Shifted Polynomial Basis

    Publication Year: 2006, Page(s):1211 - 1215
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB) | HTML iconHTML

    In this paper, we present a bit-parallel multiplier for GF(2m ) defined by an irreducible pentanomial xm+xk 3 +xk 2+xk 1+1, where 1lesk 1 lesk2 lesk3 lesm/2. In order to design an efficient, bit-parallel multiplier, we introduce a shifted polynomial basis and modify a reduction ... View full abstract»

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  • Call for papers - Special issue on Emergent Systems, Algorithms, and Architectures for Speech-Based Human-Machine Interaction

    Publication Year: 2006, Page(s): 1216
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  • TC Information for authors

    Publication Year: 2006, Page(s): c3
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  • [Back cover]

    Publication Year: 2006, Page(s): c4
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org