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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 8 • Aug. 2006

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  • Table of contents

    Publication Year: 2006, Page(s): c1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2006, Page(s): c2
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  • Guest Editorial

    Publication Year: 2006, Page(s):789 - 790
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  • Retargetable pipeline hazard detection for partially bypassed processors

    Publication Year: 2006, Page(s):791 - 801
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1059 KB) | HTML iconHTML

    Register bypassing is a widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, it has significant impact on the cycle time, area, and power consumption of the processor. Owing to the strict design constraints on the performance, cost, and the power consumption of embedded processor systems, architects seek a compromise betw... View full abstract»

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  • Overlay techniques for scratchpad memories in low power embedded processors

    Publication Year: 2006, Page(s):802 - 815
    Cited by:  Papers (32)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1618 KB) | HTML iconHTML

    Energy consumption is one of the important parameters to be optimized during the design of portable embedded systems. Thus, most of the contemporary portable devices feature low-power processors coupled with on-chip memories (e.g., caches, scratchpads). Scratchpads are better than traditional caches in terms of power, performance, area, and predictability. However, unlike caches they depend upon s... View full abstract»

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  • Exploiting statistical information for implementation of instruction scratchpad memory in embedded system

    Publication Year: 2006, Page(s):816 - 829
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1484 KB) | HTML iconHTML

    A method to both reduce energy and improve performance in a processor-based embedded system is described in this paper. Comprising of a scratchpad memory instead of an instruction cache, the target system dynamically (at runtime) copies into the scratchpad code segments that are determined to be beneficial (in terms of energy efficiency and/or speed) to execute from the scratchpad. We develop a he... View full abstract»

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  • Expression equivalence checking using interval analysis

    Publication Year: 2006, Page(s):830 - 842
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (959 KB) | HTML iconHTML

    Arithmetic expressions are the fundamental building blocks of hardware and software systems. An important problem in computational theory is to decide if two arithmetic expressions are equivalent. However, the general problem of equivalence checking, in digital computers, belongs to the NP Hard class of problems. Moreover, existing general techniques for solving this decision problem are applicabl... View full abstract»

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  • Probabilistic delay budget assignment for synthesis of soft real-time applications

    Publication Year: 2006, Page(s):843 - 853
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (995 KB) | HTML iconHTML

    Unlike their hard real-time counterparts, soft real-time applications are only expected to guarantee their "expected delay" over input data space. This paradigm shift calls for customized statistical design techniques to replace the conventional pessimistic worst case analysis methodologies. We present a novel statistical time-budgeting algorithm to translate the application expected delay constra... View full abstract»

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  • SHIM: a deterministic model for heterogeneous embedded systems

    Publication Year: 2006, Page(s):854 - 867
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (587 KB) | HTML iconHTML

    Typical embedded hardware/software systems are implemented using a combination of C and an HDL such as Verilog. While each is well-behaved in isolation, combining the two gives a nondeterministic model of computation whose ultimate behavior must be validated through expensive (cycle-accurate) simulation. We propose an alternative for describing such systems. Our software/hardware integration mediu... View full abstract»

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  • Scenario-oriented design for single-chip heterogeneous multiprocessors

    Publication Year: 2006, Page(s):868 - 880
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1161 KB) | HTML iconHTML

    Single-chip heterogeneous multiprocessors (SCHMs) are arising to meet the computational demands of portable and handheld devices. These computing systems are not fully custom designs traditionally targeted by the design automation community, general-purpose designs traditionally targeted by the computer architecture community, nor pure embedded designs traditionally targeted by the real-time commu... View full abstract»

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  • An automated design tool for analog layouts

    Publication Year: 2006, Page(s):881 - 894
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2228 KB) | HTML iconHTML

    In this paper, a layout synthesis tool for the design of analog integrated circuits (ICs) is presented. This tool offers great flexibility that allows analog circuit designers to bring their special design knowledge and experiences into the synthesis process to create high-quality analog circuit layouts. Different from conventional layout systems that are limited to the optimization of single devi... View full abstract»

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  • Low-power high-performance nand match line content addressable memories

    Publication Year: 2006, Page(s):895 - 905
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1375 KB) | HTML iconHTML

    Content addressable memory (CAM) is used in fully associative VLSI lookup circuits for cache memory, translation lookaside buffers (TLBs), and in Internet Protocol (IP) address comparison. In this paper, the use of dynamic nand match lines is investigated and compared to conventional nor match lines in cache applications. To achieve high speed, a hierarchical match line is used. The dynamic stack ... View full abstract»

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  • Placement for large-scale floating-gate field-programable analog arrays

    Publication Year: 2006, Page(s):906 - 910
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (289 KB) | HTML iconHTML

    Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. Our goal in this paper is to develop the first placement algorithm for large-scale floating-gate-based FPAAs with a focus on the minimization of the parasitic effects on interconnects under various device-related constraints. Our FPA... View full abstract»

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  • Virtual memory window for application-specific reconfigurable coprocessors

    Publication Year: 2006, Page(s):910 - 915
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB) | HTML iconHTML

    The complexity of hardware/software (HW/SW) interfacing and the lack of portability across different platforms, restrain the widespread use of reconfigurable accelerators and limit the designer productivity. Furthermore, communication between SW and HW parts of codesigned applications are typically exposed to SW programmers and HW designers. In this work, we introduce a virtualization layer that a... View full abstract»

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  • New degree computationless modified euclid algorithm and architecture for Reed-Solomon decoder

    Publication Year: 2006, Page(s):915 - 920
    Cited by:  Papers (39)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (302 KB) | HTML iconHTML

    This paper proposes a new degree computationless modified Euclid (DCME) algorithm and its dedicated architecture for Reed-Solomon (RS) decoder. This architecture has low hardware complexity compared with conventional modified Euclid (ME) architectures, since it can completely remove the degree computation and comparison circuits. The architecture employing a systolic array requires only the latenc... View full abstract»

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  • 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)

    Publication Year: 2006, Page(s): 921
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  • Explore IEL IEEE's most comprehensive resource [advertisement]

    Publication Year: 2006, Page(s): 922
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  • IEEE order form for reprints

    Publication Year: 2006, Page(s): 923
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    Publication Year: 2006, Page(s): 924
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2006, Page(s): c3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2006, Page(s): c4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu