# IEEE Transactions on Electron Devices

## Filter Results

Displaying Results 1 - 25 of 33

Publication Year: 2006, Page(s):c1 - c4
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2006, Page(s): c2
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• ### Copper-Airbridged Low-Noise GaAs PHEMT With$hboxTi/hboxWN_x/hboxTi$Diffusion Barrier for High-Frequency Applications

Publication Year: 2006, Page(s):1753 - 1758
Cited by:  Papers (3)  |  Patents (14)
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A GaAs pseudomorphic HEMT (PHEMT) with Cu-metallized interconnects was successfully developed. Sputtered WNx was used as the diffusion barrier and Ti was used as the adhesion layer to improve the adhesion between WNx/Cu interface in the thin-metal structure. After copper metallization, the PHEMTs were passivated with silicon nitride to avoid copper oxidation. The Cu-airbridge... View full abstract»

• ### Investigation of Thermal Stability in Multifinger GaInP/GaAs Collector-Up Tunneling&#8211;Collector HBTs With Subtransistor Via-Hole Structure

Publication Year: 2006, Page(s):1759 - 1767
Cited by:  Papers (10)
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In this paper, thermal stability in the multifinger GaInP/GaAs collector-up tunneling-collector heterojunction bipolar transistors (C-up TC-HBTs) has been investigated. Two unique structures in these C-up TC-HBTs are provided for thermal management for a stable operation. One is the base layer that is incorporated with highly resistive regions, which serves as a ballast resistor, due to the boron-... View full abstract»

• ### Simulation of Electron Transport in InGaAs/AlGaAs HEMTs Using an Electrothermal Monte Carlo Method

Publication Year: 2006, Page(s):1768 - 1774
Cited by:  Papers (29)
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The electrothermal simulator developed in this work uses an iterative procedure that self-consistently couples a Monte Carlo electronic trajectory simulation with a fast Fourier series solution of the heat diffusion equation. Results presented in this paper are obtained from the simulation of In0.15Ga0.85As/Al 0.28Ga0.72As HEMTs. The negative differentia... View full abstract»

• ### Determination of Density of States in Amorphous Carbon

Publication Year: 2006, Page(s):1775 - 1781
Cited by:  Papers (3)
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Various methods have been employed before to deduce the density of states (DOS) in amorphous carbon. However, further investigations show that capacitance measurements on a metal-insulator-semiconductor structure are an appropriate way to deduce the DOS. Thus, an analytical formalism, which agrees well with the experimental data, is developed. This paper reports the structures and techniques used ... View full abstract»

• ### A Three-Dimensional Simulation Study of the Performance of Carbon Nanotube Field-Effect Transistors With Doped Reservoirs and Realistic Geometry

Publication Year: 2006, Page(s):1782 - 1788
Cited by:  Papers (55)
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This paper simulates the expected device performance and scaling perspectives of carbon nanotube (CNT) field-effect transistors with doped source and drain extensions. The simulations are based on the self-consistent solution of the three-dimensional Poisson-Schroumldinger equation with open boundary conditions, within the nonequilibrium Green's function formalism, where arbitrary gate geometry an... View full abstract»

• ### Active-Matrix Amorphous-Silicon TFTs Arrays at 180$^circhboxC$on Clear Plastic and Glass Substrates for Organic Light-Emitting Displays

Publication Year: 2006, Page(s):1789 - 1796
Cited by:  Papers (17)  |  Patents (7)
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An amorphous-silicon thin-film transistor (TFT) process with a 180 degC maximum temperature using plasma-enhanced chemical vapor deposition has been developed on both novel clear polymer and glass substrates. The gate leakage current, threshold voltage, mobility, and on/off ratio of the TFTs are comparable with those of standard TFTs on glass with deposition temperature of 300 degC-350 degC. Activ... View full abstract»

• ### Higher Order Autocorrelation Vision Chip

Publication Year: 2006, Page(s):1797 - 1804
Cited by:  Papers (22)
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This paper describes very large scale integration implementation using a new vision chip architecture specialized for target tracking and recognition. A 64 times 64 pixel prototype vision chip and its evaluation results are shown. The extraction algorithms of both higher order local autocorrelation (HLAC) features and moment features are implemented on the prototype chip in order to achieve high-s... View full abstract»

• ### Mechanism of Dynamic Bias Temperature Instability in p- and nMOSFETs: The Effect of Pulse Waveform

Publication Year: 2006, Page(s):1805 - 1814
Cited by:  Papers (12)
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The waveform effect on dynamic bias temperature instability (BTI) is systematically studied for both p- and nMOSFETs with ultrathin SiON gate dielectrics by using a modified direct-current current-voltage method to monitor the stress-induced interface trap density. Interface traps are generated at the inversion gate bias (negative for pMOSFETs and positive for nMOSFETs) and are partially recovered... View full abstract»

• ### Gate Bias Effect on the 60-MeV Proton Irradiation Response of 65-nm CMOS nMOSFETs

Publication Year: 2006, Page(s):1815 - 1820
Cited by:  Papers (2)
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The response to a 60-MeV proton irradiation of nMOSFETs fabricated in a 65-nm CMOS technology using a 1.4-nm gate oxide is reported. A strong dependence on the gate bias during the exposure is found. Whereas no degradation is observed for 0-V bias, soft or hard breakdown occurs under normal operational conditions, i.e., 1.2 V on the gate. Furthermore, it is noted that the breakdown happens prefere... View full abstract»

• ### $hboxN_2$-Annealing Effects on Characteristics of Schottky-Barrier MOSFETS

Publication Year: 2006, Page(s):1821 - 1825
Cited by:  Papers (22)
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Schottky-barrier (SB) heights of erbium and platinum silicides are evaluated using current-voltage and capacitance-voltage methods in the Schottky diodes. For the erbium-silicided Schottky diodes, the extracted SB heights show big differences depending on the extraction methods, due to the existence of the interface traps. The interface traps in the erbium silicide are efficiently cured by N2... View full abstract»

• ### Fabrication of FinFETs by Damage-Free Neutral-Beam Etching Technology

Publication Year: 2006, Page(s):1826 - 1833
Cited by:  Papers (19)  |  Patents (1)
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A high aspect ratio and damage-free vertical ultrathin channel for a vertical-type double-gate MOSFET was fabricated by using low-energy neutral-beam etching (NBE). NBE can completely eliminate the charge build-up and photon-radiation damages caused by the plasma. The fabricated FinFETs realize a higher device performance (i.e., higher electron mobility) than that obtained by using a conventional ... View full abstract»

• ### Enhanced Carbon Confinement of Ultranarrow Boron Profiles in SiGeC HBTs

Publication Year: 2006, Page(s):1834 - 1839
Cited by:  Papers (3)  |  Patents (3)
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This paper reports on observations of enhanced carbon confinement of ultranarrow boron profiles in silicon-germanium-carbon heterojunction bipolar transistors (SiGeC HBTs). Electrical measurements of HBT devices with base regions formed during a low-pressure chemical-vapor deposition, with this method shows that a current gain (beta) is increased, base sheet resistance (Rbs) is reduced,... View full abstract»

• ### Physics of Hole Transport in Strained Silicon MOSFET Inversion Layers

Publication Year: 2006, Page(s):1840 - 1851
Cited by:  Papers (102)  |  Patents (3)
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A comprehensive quantum anisotropic transport model for holes was used to study silicon PMOS inversion layer transport under arbitrary stress. The anisotropic band structures of bulk silicon and silicon under field confinement as a twodimensional quantum gas are computed using the pseudopotential method and a six-band stress-dependent k.p Hamiltonian. Anisotropic scattering is included in the mome... View full abstract»

• ### Static and Dynamic TCAD Analysis of IMOS Performance: From the Single Device to the Circuit

Publication Year: 2006, Page(s):1852 - 1857
Cited by:  Papers (30)
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Impact ionization MOSFET (IMOS) is a device that enables to reach subthreshold slopes as small as 5 mV/dec. This device has an asymmetric doping profile, and only a fraction of the channel is covered by the gate. In the first part of this paper, the purpose is to investigate the impact of some geometrical parameters on the IMOS performance: the gate length, the intrinsic length, and the Si film th... View full abstract»

• ### Charge Trapping in High-$k$Gate Stacks Due to the Bilayer Structure Itself

Publication Year: 2006, Page(s):1858 - 1867
Cited by:  Papers (23)
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Charge trapping at the interface between the two dielectric layers of a high-k gate stack is shown to be caused by Maxwell-Wagner instability, which is the following. The fact that the high-k and interfacial layers have different compositions means that they will also have different conductivities. Then, a gate bias will produce a discontinuity in current at their interface, causing charge to accu... View full abstract»

• ### Modeling and Data for Thermal Conductivity of Ultrathin Single-Crystal SOI Layers at High Temperature

Publication Year: 2006, Page(s):1868 - 1876
Cited by:  Papers (57)
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Simulations of the temperature field in silicon-on-insulator (SOI) and strained-Si transistors can benefit from experimental data and modeling of the thin silicon layer thermal conductivity at high temperatures. This paper develops algebraic expressions to account for the reduction in thermal conductivity due to the phonon-boundary scattering for pure and doped silicon layers and presents the expe... View full abstract»

• ### Work Function Tuning and Material Characteristics of Lanthanide-Incorporated Metal Nitride Gate Electrodes for NMOS Device Applications

Publication Year: 2006, Page(s):1877 - 1884
Cited by:  Papers (7)  |  Patents (1)
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A versatile method to tune the work function PhiM of metal nitride (MNx) metal gates by incorporating lanthanide elements for the applications in NMOS devices is demonstrated. By incorporating lanthanide elements such as terbium (Tb), erbium (Er), or ytterbium (Yb) into MNx metal gates such as TaN and HfN, the work function of these MNx can be tuned cont... View full abstract»

• ### Physical Model for the Resistivity and Temperature Coefficient of Resistivity in Heavily Doped Polysilicon

Publication Year: 2006, Page(s):1885 - 1892
Cited by:  Papers (20)  |  Patents (1)
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One of the key benefits of using polysilicon as the material for resistors and piezoresistors is that the temperature coefficient of resistivity (TCR) can be tailored to be negative, zero, or positive by adjusting the doping concentration. This paper focuses on optimization of the boron doping of low-pressure chemical vapor deposited polysilicon resistors for obtaining near-zero TCR and developmen... View full abstract»

• ### P-Type Versus n-Type Silicon Wafers: Prospects for High-Efficiency Commercial Silicon Solar Cells

Publication Year: 2006, Page(s):1893 - 1901
Cited by:  Papers (62)  |  Patents (5)
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Chemical and crystallographic defects are a reality of solar-grade silicon wafers and industrial production processes. Long overlooked, phosphorus as a bulk dopant in silicon wafers is an excellent way to mitigate recombination associated with these defects. This paper details the connection between defect recombination and solar cell terminal characteristics for the specific case of unequal elect... View full abstract»

• ### High-Frequency and Noise Performances of 65-nm MOSFET at Liquid Nitrogen Temperature

Publication Year: 2006, Page(s):1902 - 1908
Cited by:  Papers (14)
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In this paper, the high-frequency properties of MOSFETs at low-temperature operation are investigated through measurements and electrical simulations. The experimental results show that the device achieves a 335-GHz fmax and a 300-GHz ft when operating at low temperature (78 K), which constitutes, respectively, a 78% and 34% improvement compared to the room temperature perfor... View full abstract»

• ### New Superjunction LDMOST With N-Buffer Layer

Publication Year: 2006, Page(s):1909 - 1913
Cited by:  Papers (26)
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A buffered superjunction LDMOST (SJ-LDMOST) structure, which reduces substrate-assisted depletion effects, is proposed and the experimental implementation in a CMOS technology are presented. The proposed structure uses an N-buffer layer between the pillars and the P-substrate to achieve charge compensation between the pillars, the N-buffer layer, and the P-substrate. The practical implementation i... View full abstract»

• ### Extraction of the Inversion and Accumulation Layer Mobilities in n-Channel Trench DMOSFETs

Publication Year: 2006, Page(s):1914 - 1921
Cited by:  Papers (7)
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A new method to extract both the inversion and accumulation layer mobilities of electrons in n-channel trench double-diffused MOSFETs (DMOSFETs) is proposed and implemented for the first time. First, a model is developed for the on-resistance of the n-channel trench DMOSFET. This on-resistance model is fitted to the experimental data measured from an experimental n-channel trench DMOSFET by the me... View full abstract»

• ### Dynamics of Retrograde Electrons Returning From the Output Cavity in Klystrons

Publication Year: 2006, Page(s):1922 - 1928
Cited by:  Papers (9)
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Loss of efficiency and tube oscillations have been attributed to electrons returning from the output cavity in klystrons due to excessive output cavity voltages. It is generally believed that the retrograde electrons lead to a relatively large harmonic current component in the input cavity, which overwhelms the input drive. Here, for the first time, detailed simulations describing the dynamics of ... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy