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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 7 • Date July 2006

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  • Table of contents

    Publication Year: 2006 , Page(s): c1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2006 , Page(s): c2
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  • Guest Editorial

    Publication Year: 2006 , Page(s): 665 - 666
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  • Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia

    Publication Year: 2006 , Page(s): 667 - 680
    Cited by:  Papers (21)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1433 KB) |  | HTML iconHTML  

    The MultiFlex system is an application-to-platform mapping tool that integrates heterogeneous parallel components-H/W or S/W- into a homogeneous platform programming environment. This leads to higher quality designs through encapsulation and abstraction. Two high-level parallel programming models are supported by the following MultiFlex platform mapping tools: a distributed system object component... View full abstract»

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  • Efficient exploration of bus-based system-on-chip architectures

    Publication Year: 2006 , Page(s): 681 - 692
    Cited by:  Papers (4)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1556 KB) |  | HTML iconHTML  

    Separation between computation and communication in system design allows system designers to explore the communication architecture independently after component selection and mapping decision is made. In this paper, we present an iterative two-step exploration methodology for bus-based on-chip communication architecture for multitask applications. We assume that the memory traces from the process... View full abstract»

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  • "It's a small world after all": NoC performance optimization via long-range link insertion

    Publication Year: 2006 , Page(s): 693 - 706
    Cited by:  Papers (84)  |  Patents (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (2855 KB) |  | HTML iconHTML  

    Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture which is neither regular nor fully customized. Instead, the communication architecture we pro... View full abstract»

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  • Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation

    Publication Year: 2006 , Page(s): 707 - 716
    Cited by:  Papers (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1465 KB) |  | HTML iconHTML  

    In multiprocessor-based system-on-chips (SOCs), optimizing the communication architecture is often as important as, if not more than, optimizing the computation architecture. While there are mature platforms and techniques for the modeling and evaluation of computation architectures, the same is not true for the communication architectures. A major challenge in modeling the communication architect... View full abstract»

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  • Energy minimization for real-time systems with (m,k)-guarantee

    Publication Year: 2006 , Page(s): 717 - 729
    Cited by:  Papers (6)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (709 KB) |  | HTML iconHTML  

    Energy consumption and quality of service (QoS) are two primary concerns in the development of today's pervasive computing systems. While most of the current research in energy-aware real-time scheduling has been focused on hard real-time systems, a large number of practical applications and systems exhibit more soft real-time nature. In this paper, we study the problem of minimizing energy for so... View full abstract»

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  • System-level power-performance tradeoffs for reconfigurable computing

    Publication Year: 2006 , Page(s): 730 - 739
    Cited by:  Papers (2)  |  Patents (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1730 KB) |  | HTML iconHTML  

    In this paper, we propose a configuration-aware data-partitioning approach for reconfigurable computing. We show how the reconfiguration overhead impacts the data-partitioning process. Moreover, we explore the system-level power-performance tradeoffs available when implementing streaming embedded applications on fine-grained reconfigurable architectures. For a certain group of streaming applicatio... View full abstract»

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  • A table masking countermeasure for low-energy secure embedded systems

    Publication Year: 2006 , Page(s): 740 - 753
    Cited by:  Papers (8)  |  Patents (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1821 KB) |  | HTML iconHTML  

    Future wireless embedded devices will be increasingly powerful, supporting many more applications, including one of the most crucial, which is security. Although many embedded devices offer more resistance to bus probing attacks due to their compact size, susceptibility to power or electromagnetic analysis attacks must be analyzed. This paper presents a table masking countermeasure to resist diffe... View full abstract»

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  • ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors

    Publication Year: 2006 , Page(s): 754 - 762
    Cited by:  Papers (10)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1316 KB) |  | HTML iconHTML  

    Customization of processor architectures through instruction set extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-quality ISE generation approach needs to obtain results close to those achieved by experienced designers, particularly for complex applications that exhibit regularity: expert designers are able to exploit manually such regu... View full abstract»

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  • Extraction error modeling and automated model debugging in high-performance custom designs

    Publication Year: 2006 , Page(s): 763 - 776
    Cited by:  Papers (1)  |  Patents (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (788 KB) |  | HTML iconHTML  

    In the design cycle of high-performance integrated circuits, it is common that certain components are designed directly at the transistor level. This level of design representation may not be appropriate for test generation tools that usually require a model expressed at the gate level. Logic extraction is a key step in test model generation to produce a gate-level netlist from the transistor-leve... View full abstract»

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  • DSM interconnects: importance of inductance effects and corresponding range of length

    Publication Year: 2006 , Page(s): 777 - 779
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (230 KB) |  | HTML iconHTML  

    To analyze at which rise/fall times the inductance effect appears in DSM interconnects, the author develops a methodology versus the input line transition time to be technology-independent. These lines are modeled as RC and RLC distributed lines, and the two models are compared to define the effects caused by neglecting inductance. The goal of this study is, based upon the discrepancy between RC a... View full abstract»

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  • Instruction buffering for nested loops in low-power design

    Publication Year: 2006 , Page(s): 780 - 784
    Cited by:  Papers (5)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (213 KB) |  | HTML iconHTML  

    Several loop-buffering techniques were proposed for reducing power consumption of embedded processors. Although the schemes are effective in reducing power, they work for unnested loops (or the inner-most loop in nested loops) only. In this paper, we propose a stack-based controller which can handle sequential loops being nested in a loop of all styles and the if-then-else construct inside of a lo... View full abstract»

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  • 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)

    Publication Year: 2006 , Page(s): 785
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  • Quality without compromise [advertisement]

    Publication Year: 2006 , Page(s): 786
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  • Leading the field since 1884 [advertisement]

    Publication Year: 2006 , Page(s): 787
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    Publication Year: 2006 , Page(s): 788
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2006 , Page(s): c3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2006 , Page(s): c4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu