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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 6 • Date June 2006

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Displaying Results 1 - 19 of 19
  • Table of contents

    Publication Year: 2006 , Page(s): c1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2006 , Page(s): c2
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  • Automatic linearity and frequency response tests with built-in pattern generator and analyzer

    Publication Year: 2006 , Page(s): 561 - 572
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (610 KB) |  | HTML iconHTML  

    We present a built-in self-test (BIST) approach based on a direct digital synthesizer (DDS) for functionality testing of analog circuitry in mixed-signal systems. A main contribution of this paper is the BIST-based hardware implementation and measurement of amplifier linearity (IP3) and frequency response, including both phase and gain. The approach has been implemented in Verilog and synthesized ... View full abstract»

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  • Design techniques and test methodology for low-power TCAMs

    Publication Year: 2006 , Page(s): 573 - 586
    Cited by:  Papers (15)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1889 KB) |  | HTML iconHTML  

    Ternary content addressable memories (TCAMs) are gaining importance in high-speed lookup-intensive applications. However, the high cost and power consumption are limiting their popularity and versatility. TCAM testing is also time consuming due to the complex integration of logic and memory. In this paper, we present a comprehensive review of the design techniques for low-power TCAMs. We also prop... View full abstract»

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  • Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits

    Publication Year: 2006 , Page(s): 587 - 595
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (471 KB) |  | HTML iconHTML  

    Partially depleted silicon-on-insulator (PD-SOI) technology has garnered more attention recently with regards to replacing traditional bulk-silicon technology as the mainstream technology of choice for high-performance/low-power digital applications. The increase in performance is due to the buried oxide layer, which provides a dramatic decrease in the source and drain junction capacitance, as wel... View full abstract»

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  • The LOTTERYBUS on-chip communication architecture

    Publication Year: 2006 , Page(s): 596 - 608
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1247 KB) |  | HTML iconHTML  

    On-chip communication architectures play an important role in determining the overall performance of System-on-Chip (SoC) designs. Communication architectures should be flexible so as to offer high performance over a wide range of traffic characteristics. In particular, the resource sharing mechanism of the communication architecture, which determines how the often-conflicting requirements of diff... View full abstract»

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  • Architectural enhancements for network congestion control applications

    Publication Year: 2006 , Page(s): 609 - 615
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (786 KB) |  | HTML iconHTML  

    Complex network protocols and various network services require significant processing capability for modern network applications. One of the important features in modern networks is differentiated service. Along with differentiated service, rapidly changing network environments result in congestion problems. In this paper, we analyze the characteristics of representative congestion control applica... View full abstract»

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  • Power minimization for dynamic PLAs

    Publication Year: 2006 , Page(s): 616 - 624
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1166 KB) |  | HTML iconHTML  

    Dynamic programmable logic arrays (PLAs) which are built of the nor-nor structure, have been very popular in high performance design because of their high-speed and predictable routing delay. However, the nor-nor structure incurs high switching activity in product lines and, thus, results in large power consumption. In this paper, we propose a new dynamic PLA structure which incorporates super pro... View full abstract»

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  • Energy efficient watermarking on mobile devices using proxy-based partitioning

    Publication Year: 2006 , Page(s): 625 - 636
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1629 KB) |  | HTML iconHTML  

    Digital watermarking embeds an imperceptible signature or watermark in a digital file containing audio, image, text, or video data. The watermark can be used to authenticate the data file and for tamper detection. It is particularly valuable in the use and exchange of digital media, such as audio and video, on emerging handheld devices. However, watermarking is computationally expensive and adds t... View full abstract»

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  • Realistic scalability of noise in dynamic circuits

    Publication Year: 2006 , Page(s): 637 - 641
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (218 KB) |  | HTML iconHTML  

    The usage of noise-sensitive dynamic circuits has become commonplace due to speed and area requirements, making the noise issue even more prominent. This paper focuses on the trends of coupling and its effects on dynamic circuits. It presents closed form analytical solutions for noise, as well as noise tolerance metrics for dynamic circuits. These solutions are within 5% of dynamic simulations. It... View full abstract»

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  • Crosstalk modeling for coupled RLC interconnects with application to shield insertion

    Publication Year: 2006 , Page(s): 641 - 646
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (344 KB) |  | HTML iconHTML  

    On-chip interconnect delay and crosstalk noise have become significant bottlenecks in the performance and signal integrity of deep submicrometer VLSI circuits. A crosstalk noise model for both identical and nonidentical coupled resistance-inductance-capacitance (RLC) interconnects is developed based on a decoupling technique exhibiting an average error of 6.8% as compared to SPICE. The crosstalk n... View full abstract»

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  • A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits

    Publication Year: 2006 , Page(s): 646 - 649
    Cited by:  Papers (35)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (677 KB) |  | HTML iconHTML  

    This paper describes a process compensating dynamic (PCD) circuit technique for maintaining the performance benefit of dynamic circuits and reducing the variation in delay and robustness. A variable strength keeper that is optimally programmed based on the die leakage, enables 10% faster performance, 35% reduction in delay variation, and 5times reduction in the number of robustness failing dies, c... View full abstract»

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  • MICRO: a new hybrid test data compression/decompression scheme

    Publication Year: 2006 , Page(s): 649 - 654
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (575 KB) |  | HTML iconHTML  

    To overcome the limitation of the automatic test equipment (ATE), test data compression/decompression schemes become a more important issue of testing for a system-on-chip (SoC). In order to alleviate the limitation of previous works, a new hybrid test data compression/decompression scheme for an SoC is developed. The new scheme is based on analyzing the factors that influence test parameters: com... View full abstract»

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  • Wafer-level package interconnect options

    Publication Year: 2006 , Page(s): 654 - 659
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (758 KB) |  | HTML iconHTML  

    As integrated circuit technology enters the nanometer era, global interconnects are becoming a bottleneck for overall chip performance. In this paper, we show that wafer-level package interconnects are an effective alternative to conventional on-chip global wires. These interconnects behave as LC transmission lines and can be exploited for their near speed of light transmission and low attenuation... View full abstract»

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  • Design of flexible GF(2/sup m/) elliptic curve cryptography processors

    Publication Year: 2006 , Page(s): 659 - 662
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (444 KB) |  | HTML iconHTML  

    The design of flexible elliptic curve cryptography processors (ECP) is considered in this paper. Novel word-level algorithms and implementations for the underlying GF(2m) multiplication and squaring arithmetic which enable improved flexibility versus performance tradeoffs, are presented and employed in the design of an efficient flexible ECP architecture; corresponding field-programmabl... View full abstract»

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  • 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)

    Publication Year: 2006 , Page(s): 663
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  • Have you visited lately? www.ieee.org [advertisement]

    Publication Year: 2006 , Page(s): 664
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2006 , Page(s): c3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2006 , Page(s): c4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels.

To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded. The editorial board, consisting of international experts, invites original papers which emphasize the novel system integration aspects of microelectronic systems, including interactions among system design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and system level qualification. Thus, the coverage of this Transactions focuses on VLSI/ULSI microelectronic system integration.

Topics of special interest include, but are not strictly limited to, the following: • System Specification, Design and Partitioning, • System-level Test, • Reliable VLSI/ULSI Systems, • High Performance Computing and Communication Systems, • Wafer Scale Integration and Multichip Modules (MCMs), • High-Speed Interconnects in Microelectronic Systems, • VLSI/ULSI Neural Networks and Their Applications, • Adaptive Computing Systems with FPGA components, • Mixed Analog/Digital Systems, • Cost, Performance Tradeoffs of VLSI/ULSI Systems, • Adaptive Computing Using Reconfigurable Components (FPGAs) 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu