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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 5 • Date May 2006

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Displaying Results 1 - 18 of 18
  • Table of contents

    Publication Year: 2006, Page(s): c1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2006, Page(s): c2
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  • An analytical model for predicting the remaining battery capacity of lithium-ion batteries

    Publication Year: 2006, Page(s):441 - 451
    Cited by:  Papers (57)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (691 KB) | HTML iconHTML

    Predicting the residual energy of the battery source that powers a portable electronic device is imperative in designing and applying an effective dynamic power management policy for the device. This paper starts up by showing that a 30% error in predicting the battery capacity of a lithium-ion battery can result in up to 20% performance degradation for a dynamic voltage and frequency scaling algo... View full abstract»

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  • Energy consumption in RC tree circuits

    Publication Year: 2006, Page(s):452 - 461
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (641 KB) | HTML iconHTML

    In this paper, resistance-capacitance (RC) tree networks are modeled in terms of their energy consumption associated with an input transition. This work significantly extends the results that the same authors previously obtained in the specific case of ladder networks with only ramp signals. The proposed approach to model the energy consumption is based on a single-pole approximation, in which an ... View full abstract»

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  • Using bus-based connections to improve field-programmable gate-array density for implementing datapath circuits

    Publication Year: 2006, Page(s):462 - 473
    Cited by:  Papers (17)  |  Patents (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (654 KB) | HTML iconHTML

    As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are increasingly being used to implement large arithmetic-intensive applications, which often contain a large proportion of datapath circuits. Since datapath circuits usually consist of regularly structured components (called bit-slices) which are connected together by regularly structured signals (called buses), it is... View full abstract»

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  • Product-term-based synthesizable embedded programmable logic cores

    Publication Year: 2006, Page(s):474 - 488
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1452 KB) | HTML iconHTML

    As integrated circuits become increasingly complex, the ability to make post-fabrication changes will become more important and attractive. This capability can be realized by using programmable logic cores. Currently, such cores are available from vendors in the form of "hard" macro layouts. Previous work has suggested an alternative approach: vendors supply a synthesizable version of their progra... View full abstract»

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  • Multi-symbol-sliced dynamically reconfigurable Reed-Solomon decoder design based on unified finite-field processing element

    Publication Year: 2006, Page(s):489 - 500
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1486 KB) | HTML iconHTML

    Reed-Solomon (RS) codes play an important role in providing the error correction and the data integrity in various communication/storage applications. For high-speed applications, most RS decoders are implemented as dedicated application-specified integrated circuits (ASICs) based on parallel architectures, which can deliver high data throughput rate. For lower-speed applications, the RS decoding ... View full abstract»

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  • HotSpot: a compact thermal modeling methodology for early-stage VLSI design

    Publication Year: 2006, Page(s):501 - 513
    Cited by:  Papers (265)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1481 KB) | HTML iconHTML

    This paper presents HotSpot-a modeling methodology for developing compact thermal models based on the popular stacked-layer packaging scheme in modern very large-scale integration systems. In addition to modeling silicon and packaging layers, HotSpot includes a high-level on-chip interconnect self-heating power and thermal model such that the thermal impacts on interconnects can also be considered... View full abstract»

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  • Analysis and optimization of nanometer CMOS circuits for soft-error tolerance

    Publication Year: 2006, Page(s):514 - 524
    Cited by:  Papers (37)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1101 KB) | HTML iconHTML

    Nanometer circuits are becoming increasingly susceptible to soft errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and supply/threshold voltage scaling reduces noise margins. It is becoming crucial to add soft-error tolerance estimation and optimization to the design flow to handle the increasing susceptibility. The first part of this paper pr... View full abstract»

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  • Code compression for embedded VLIW processors using variable-to-fixed coding

    Publication Year: 2006, Page(s):525 - 536
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (727 KB) | HTML iconHTML

    In embedded system design, memory is one of the most restricted resources, posing serious constraints on program size. Code compression has been used as a solution to reduce the code size for embedded systems. Lossless data compression techniques are used to compress instructions, which are then decompressed on-the-fly during execution. Previous work used fixed-to-variable coding algorithms that t... View full abstract»

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  • Diagnosis of logic circuits using compressed deterministic data and on-chip response comparison

    Publication Year: 2006, Page(s):537 - 548
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (934 KB) | HTML iconHTML

    While manufacturing test helps to isolate faulty devices from the good ones, diagnosis is enabling a faster transition from the yield learning to the volume production phase of a new process technology. Given the escalating design complexity, new methods such as embedded deterministic test have been proposed in recent years to deal with the cost of manufacturing test. This paper discusses diagnosi... View full abstract»

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  • A leakage-tolerant low-swing circuit style in partially depleted silicon-on-insulator CMOS technologies

    Publication Year: 2006, Page(s):549 - 552
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (199 KB) | HTML iconHTML

    The parasitic bipolar leakage and the large subthreshold leakage due to high floating-body voltage reduce the noise margin and increase the delay of the circuits in the partially depleted silicon-on-insulator (PD/SOI). Differential cascode voltage switch logic (DCVSL) has circuit topologies susceptible to the leakage currents. In this paper, we propose a new circuit style to effectively handle the... View full abstract»

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  • Multi-objective module placement for 3-D system-on-package

    Publication Year: 2006, Page(s):553 - 557
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (502 KB) | HTML iconHTML

    System-on-package (SOP) is a viable alternative to system-on-chip (SOC) for meeting the rigorous requirements of today's mixed-signal system integration. Thermal integrity is arguably the most crucial issue in three-dimensional (3-D) SOP due to the compact nature of the 3-D integration. In addition, the power supply noise issue becomes more serious as the supply voltage continues to decrease while... View full abstract»

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  • Special section on autonomous silicon validation and testing of microprocessors and microprocessor-based systems

    Publication Year: 2006, Page(s): 558
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  • Special section on system on chip integration

    Publication Year: 2006, Page(s): 559
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  • Quality without compromise [advertisement]

    Publication Year: 2006, Page(s): 560
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2006, Page(s): c3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2006, Page(s): c4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu