IEEE Computer Architecture Letters

Issue 1 • January-December 2004

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Displaying Results 1 - 9 of 9
  • Exploiting Low Entropy to Reduce Wire Delay

    Publication Year: 2004, Page(s): 1
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (200 KB) | HTML iconHTML

    Wires shrink less efficiently than transistors. Smaller dimensions increase relative delay and the probability of crosstalk. Solutions to this problem include adding additional latency with pipelining, using "fat wires" at higher metal levels, and advances in process and material technology. We propose a stopgap solution to this problem by applying a decade old technique called bus-expanding to th... View full abstract»

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  • Globally Adaptive Load-Balanced Routing on Tori

    Publication Year: 2004, Page(s): 2
    Cited by:  Papers (41)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (144 KB) | HTML iconHTML

    We introduce a new method of adaptive routing on k-ary n-cubes, Globally Adaptive Load-Balance (GAL). GAL makes global routing decisions using global information. In contrast, most previous adaptive routing algorithms make local routing decisions using local information (typically channel queue depth). GAL senses global congestion using segmented injection queues to decide the directions to route ... View full abstract»

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  • An Efficient Fault-Tolerant Routing Methodology for Meshes and Tori

    Publication Year: 2004, Page(s): 3
    Cited by:  Papers (33)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (136 KB) | HTML iconHTML

    In this paper we present a methodology to design fault-tolerant routing algorithms for regular direct interconnection networks. It supports fully adaptive routing, does not degrade performance in the absence of faults, and supports a reasonably large number of faults without significantly degrading performance. The methodology is mainly based on the selection of an intermediate node (if needed) fo... View full abstract»

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  • Comparing Adaptive Routing and Dynamic Voltage Scaling for Link Power Reduction

    Publication Year: 2004, Page(s): 4
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1048 KB) | HTML iconHTML

    We compare techniques that dynamically scale the voltage of individual network links to reduce power consumption with an approach in which all links in the network are set to the same voltage and adaptive routing is used to distribute load across the network. Our results show that adaptive routing with static network link voltages outperforms dimension-order routing with dynamic link voltages in a... View full abstract»

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  • Thread-Sensitive Instruction Issue for SMT Processors

    Publication Year: 2004, Page(s): 5
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (128 KB) | HTML iconHTML

    Simultaneous Multi Threading (SMT) is a processor design method in which concurrent hardware threads share processor resources like functional units and memory. The scheduling complexity and performance of an SMT processor depend on the topology used in the fetch and issue stages. In this paper, we propose a thread sensitive issue policy for a partitioned SMT processor which is based on a thread m... View full abstract»

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  • Efficiently Evaluating Speedup Using Sampled Processor Simulation

    Publication Year: 2004, Page(s): 6
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (120 KB) | HTML iconHTML

    Cycle accurate simulation of processors is extremely time consuming. Sampling can greatly reduce simulation time while retaining good accuracy. Previous research on sampled simulation has been focusing on the accuracy of CPI. However, most simulations are used to evaluate the benefit of some microarchitectural enhancement, in which the speedup is a more important metric than CPI. We employ the rat... View full abstract»

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  • CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction

    Publication Year: 2004, Page(s): 7
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (120 KB) | HTML iconHTML

    Load misses in on-chip L2 caches often end up stalling modern superscalars. To address this problem, we propose hiding L2 misses with Checkpoint-Assisted VAlue prediction (CAVA). When a load misses in L2, a predicted value is returned to the processor. If the missing load reaches the head of the reorder buffer before the requested data is received from memory, the processor checkpoints, consumes t... View full abstract»

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  • Buffer and Delay Bounds in High Radix Interconnection Networks

    Publication Year: 2004, Page(s): 8
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (160 KB) | HTML iconHTML

    We apply recent results in queueing theory to propose a methodology for bounding the buffer depth and packet delay in high radix interconnection networks. While most work in interconnection networks has been focused on the throughput and average latency in such systems, few studies have been done providing statistical guarantees for buffer depth and packet delays. These parameters are key in the d... View full abstract»

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  • Characterization of Problem Stores

    Publication Year: 2004, Page(s): 9
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (93 KB) | HTML iconHTML

    This paper introduces the concept of problem stores: static stores whose dependent loads often miss in the cache. Accurately identifying problem stores allows the early determination of addresses likely to cause later misses, potentially allowing for the development of novel, proactive prefetching and memory hierarchy management schemes. We present a detailed empirical characterization of problem ... View full abstract»

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IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. 

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Editor-in-Chief
Daniel J. Sorin
Duke University
Electrical & Computer Engineering
PO Box 90291
Durham, NC 27708
e-mail: sorin@ee.duke.edu