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Computer

Issue 3 • Date March 1973

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Displaying Results 1 - 22 of 22
  • Computer

    Page(s): c1
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  • Design Automation System for Microprogramming [advertisement]

    Page(s): c2
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  • Table of contents

    Page(s): 5
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  • 1973 International Symposium on Fault-Tolerant Computing

    Page(s): 6
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  • Update: information for the computer systems design professional

    Page(s): 7 - 9
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  • Call for Papers

    Page(s): 9
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  • On The Passing Of MOBIDIC-B

    Page(s): 10 - 18
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  • PMS: A Notaton to Describe Comuter Sructures

    Page(s): 19 - 21
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    The PMS notation was developed to describe the physical structure of computer systems in terms of a small number of elementary components for textbook (Bell and Newell, 1971). View full abstract»

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  • ISP: A Notation to Describe A Computer's Instruction Sets

    Page(s): 22 - 24
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    The ISP (for Instruction Set Processor) notation was developed for a text [Bell& Newell, 1971] to precisely describe the programming level of a computer in terms of its Memory, Instruction Format, Data Types, Data Operations, Interpreting a Specific Instruction Set. View full abstract»

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  • A Data Base For Computer Performance Evaluation

    Page(s): 25 - 29
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    We describe in this paper an RCA Labs team project begun in 1968, with the general goal to predict the performance of new system architectures being considered within RCA for future computers. The cache-system or slave memory idea was the principal subject. However, many other problems have been studied, and the data base that was collected has been found useful in analysis as well as prediction of performance, and in obtaining fundamental data for modelling purposes. View full abstract»

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  • Cache-based Computer Systems

    Page(s): 30 - 36
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    A cache-based computer system employs a fast, small memory -the " cache" - interposed between the usual processor and main memory. At any given time the cache contains as much as possible the instructions and data the processor needs; as new information is needed it is brought from main memory to cache, displacing old information. The processor tends to operate with a memory of cache speed but with main memory cost-per-bit. This configuration has analogies with other systems employing memory hierarchies, such as "paging" or "virtual memory" systems. In contrast with these latter, a cache is managed by hardware algorithms, deals with smaller blocks of data (32 bytes, for example, rather than 4096), provides a smaller ratio of memory access times (5:1 rather than 1000: 1), and, because of the last factor, holds the processor idle while blocks of data are being transferred from main memory to cache rather than switching to another task. These are important differences, and may suffice to make the cache-based system cost effective in many situations where paging is not. View full abstract»

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  • Attacking on the Flank

    Page(s): 37 - 39
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    In this exclusive interview with COMPUTER magazine, ex-IBM dean of computer architecture, Dr. Gene Amdahl, claims a new large-scale computer that is considerably faster and more efficient than any IBM, CDC or other competitor's offering. View full abstract»

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  • So you're a Computer Expert! [advertisement]

    Page(s): 40
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  • Repository [advertisement]

    Page(s): 41 - 42
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  • New Products

    Page(s): 43 - 46
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  • New Applications

    Page(s): 47 - 48
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  • Point of view

    Page(s): 49
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  • IEEE Computer Society publications

    Page(s): 50 - 51
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  • Product Profile

    Page(s): 52 - 56
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  • Computing Reviews

    Page(s): 56
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  • Pattern Recognition Data Bases Available

    Page(s): 56
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  • Computers Made Easy

    Page(s): 56
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Aims & Scope

Computer, the flagship publication of the IEEE Computer Society, publishes highly acclaimed peer-reviewed articles written for and by professionals representing the full spectrum of computing technology from hardware to software and from current research to new applications.

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Meet Our Editors

Editor-in-Chief
Ron Vetter
University of North Carolina
Wilmington