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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 8 • Date Aug. 2006

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Displaying Results 1 - 18 of 18
  • Table of contents

    Publication Year: 2006, Page(s): c1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2006, Page(s): c2
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  • Refinement-based synthesis of continuous-time analog filters through successive domain pruning, plateau search, and adaptive sampling

    Publication Year: 2006, Page(s):1421 - 1440
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB) | HTML iconHTML

    This paper presents a novel algorithm for synthesis of continuous-time analog filters. The goal is to find as many "very good" design points as possible without requiring feasible designs as starting points or any other additional designer knowledge as input. This problem is challenging for present exploration-based analog-synthesis methods, including existing commercial tools, which have difficul... View full abstract»

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  • An approach for the formal verification of DSP designs using Theorem proving

    Publication Year: 2006, Page(s):1441 - 1457
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB) | HTML iconHTML

    This paper proposes a framework for the incorporation of formal methods in the design flow of digital signal processing (DSP) systems in a rigorous way. In the proposed approach, DSP descriptions were modeled and verified at different abstraction levels using higher order logic based on the higher order logic (HOL) theorem prover. This framework enables the formal verification of DSP designs that ... View full abstract»

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  • CARH: service-oriented architecture for validating system-level designs

    Publication Year: 2006, Page(s):1458 - 1474
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB) | HTML iconHTML

    Existing system-level design languages (SLDLs) and frameworks mainly provide a modeling and a simulation framework. However, there is an increasing demand for supporting tools to aid designers in quick and faster design space and architectural exploration. As a result, numerous tools such as integrated development environments (IDEs) and others that help in debugging, visualization, validation, an... View full abstract»

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  • Gate-length biasing for runtime-leakage control

    Publication Year: 2006, Page(s):1475 - 1485
    Cited by:  Papers (26)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB) | HTML iconHTML

    Leakage power has become one of the most critical design concerns for the system level chip designer. While lowered supplies (and consequently, lowered threshold voltage) and aggressive clock gating can achieve dynamic power reduction, these techniques increase the leakage power and, therefore, causes its share of total power to increase. Manufacturers face the additional challenge of leakage vari... View full abstract»

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  • Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits

    Publication Year: 2006, Page(s):1486 - 1495
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB) | HTML iconHTML

    In nanoscale complementary metal-oxide-semiconductor (CMOS) devices, a significant increase in subthreshold, gate, and reverse-biased junction band-to-band-tunneling (BTBT) leakage results in large leakage power in logic circuits. Leakage components interact with each other at the device level (through device geometry and the doping profile) and at the circuit level (through the node voltages). Du... View full abstract»

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  • Wideband passive multiport model order reduction and realization of RLCM circuits

    Publication Year: 2006, Page(s):1496 - 1509
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (912 KB) | HTML iconHTML

    This paper presents a novel compact passive modeling technique for high-performance RF passive and interconnect circuits modeled as high-order resistor-inductor-capacitor-mutual inductance circuits. The new method is based on a recently proposed general s-domain hierarchical modeling and analysis method and vector potential equivalent circuit model for self and mutual inductances. Theoretically, t... View full abstract»

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  • Algorithms for simultaneous escape routing and Layer assignment of dense PCBs

    Publication Year: 2006, Page(s):1510 - 1522
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB) | HTML iconHTML

    As die sizes are shrinking, and circuit complexities are increasing, the printed circuit board routing problem becomes more and more challenging. Traditional routing algorithms cannot handle these challenges effectively, and many high-end designs in the industry require manual routing efforts. This paper proposes a problem decomposition that distinguishes routing under dense components from routin... View full abstract»

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  • Interconnect estimation for FPGAs

    Publication Year: 2006, Page(s):1523 - 1534
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB) | HTML iconHTML

    Interconnect planning is becoming an important design issue for large field programmable gate array (FPGA)-based designs. One of the most important issues for planning interconnection is the ability to reliably predict the routing requirements of a given design. In this paper, a new methodology, called fast generic routability estimation for placed FPGA circuits (fGREP), for fast and reliable esti... View full abstract»

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  • Pseudofunctional testing

    Publication Year: 2006, Page(s):1535 - 1546
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB) | HTML iconHTML

    Recent research results have shown that the traditional structural testing for delay and signal integrity faults may result in overtesting due to the nontrivial number of such faults that are untestable in the functional mode although testable in the test mode. This paper presents a pseudofunctional-test methodology that attempts to minimize the overtesting problem of the scan-based circuits in au... View full abstract»

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  • Entropy-driven parity-tree selection for low-overhead concurrent error detection in finite state machines

    Publication Year: 2006, Page(s):1547 - 1554
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB) | HTML iconHTML

    This paper presents discuss the problem of parity-tree selection for performing concurrent error detection (CED) with low overhead in finite state machines (FSMs). We first develop a nonintrusive CED method based on compaction of the state/output bits of an FSM via parity trees and comparison to the correct responses, which are generated through additional on-chip parity prediction hardware. Simil... View full abstract»

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  • A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs

    Publication Year: 2006, Page(s):1555 - 1564
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB) | HTML iconHTML

    In this paper, an automatic test pattern generator (ATPG)-based scan-path test point insertion technique, which can achieve high delay fault coverage for scan designs, is proposed. In the proposed technique, the shift dependency between adjacent scan flip-flops, which causes some delay faults to be untestable in the standard scan environment, is broken by inserting test points, which can be combin... View full abstract»

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  • LT-RTPG: a new test-per-scan BIST TPG for low switching activity

    Publication Year: 2006, Page(s):1565 - 1574
    Cited by:  Papers (32)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB) | HTML iconHTML

    A new built-in self-test (BIST) test pattern generator (TPG) design, called low-transition random TPG (LT-RTPG), is presented. An LT-RTPG is composed of a linear feedback shift register (LFSR), a κ-input AND gate, and a T flip-flop. When used to generate test patterns for test-per-scan BIST, it decreases the number of transitions that occur during scan shifting and, hence, decreases switchin... View full abstract»

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  • 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)

    Publication Year: 2006, Page(s): 1575
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  • IEEE Biomedical Circuits and Systems Conference healthcare technology (BiOCAS 2006)

    Publication Year: 2006, Page(s): 1576
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2006, Page(s): c3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2006, Page(s): c4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu